CAJ | 학술논문

介绍了一种新型的基于数字延迟锁定环DLL( Delay Lock Loop)技术的混合数字脉宽调制器DPWM( Digital Pulse Width Modulator)结构,该结构用可编程延迟单元PDU( Programmable Delay Unit)构成延迟线,通过DLL调节算法,动态地调整PDU的延迟时间,从而消除了延迟线的延迟时间受工艺、温度、工作电压的影响,提高了PWM的调节线性度,适用于数字控制开关式电源SMPS( Switched-Mode Power Supply),可以大幅度的提升系统的性能。同时,此种结构的DPWM适合FPGA验证和流片实现。采用CMOS 0.18μm工艺对所提出的结构进行了设计与实现,DPWM占用面积0.0457 mm2,芯片测试结果非常好,可以进行工程应用。
개소료일충신형적기우수자연지쇄정배DLL( Delay Lock Loop)기술적혼합수자맥관조제기DPWM( Digital Pulse Width Modulator)결구,해결구용가편정연지단원PDU( Programmable Delay Unit)구성연지선,통과DLL조절산법,동태지조정PDU적연지시간,종이소제료연지선적연지시간수공예、온도、공작전압적영향,제고료PWM적조절선성도,괄용우수자공제개관식전원SMPS( Switched-Mode Power Supply),가이대폭도적제승계통적성능。동시,차충결구적DPWM괄합FPGA험증화류편실현。채용CMOS 0.18μm공예대소제출적결구진행료설계여실현,DPWM점용면적0.0457 mm2,심편측시결과비상호,가이진행공정응용。
A novel digital pulse width modulator( DPWM) architecture that based on DLL technology is introduced, which applies to switched-mode power supply( SMPS) . The delay line of this DPWM take advantage of the program-mable delay unit(PDU)and the DLL technology to eliminate the influence of process,temperature and voltage, which improve the linearity of PWM dramatically. This DPWM is well suited for FPGA or custom chip implementa-tion. The IC occupying only 0.045 7 mm2 silicon area is implemented in a CMOS 0.18μm process,the measure re-sults meet with the demand and the DPWM can fit the engineering application.