CAJ | 학술논문

介绍了一种低相噪线性调频( LFM )雷达信号源的产生和实现方案。通过分析 DDS输出信号频谱和杂散,采用HMC704控制VCO的方法设计了1 GHz的锁相环路( PLL)作为DDS的时钟驱动电路,并对环路滤波器和AD9910硬件电路优化设计改善杂散和相噪性能。通过计算寄存器参数和分析SPI总线时序,利用FPGA对DDS和PLL高速配置。最后给出了系统实物图和测试方法,实测结果表明：该线性调频源输出幅度大于-3 dBm,频率步进为1 kHz,相位噪声优于-103 dBc/Hz@1 kHz,各项指标满足实际工程要求。
개소료일충저상조선성조빈( LFM )뢰체신호원적산생화실현방안。통과분석 DDS수출신호빈보화잡산,채용HMC704공제VCO적방법설계료1 GHz적쇄상배로( PLL)작위DDS적시종구동전로,병대배로려파기화AD9910경건전로우화설계개선잡산화상조성능。통과계산기존기삼수화분석SPI총선시서,이용FPGA대DDS화PLL고속배치。최후급출료계통실물도화측시방법,실측결과표명：해선성조빈원수출폭도대우-3 dBm,빈솔보진위1 kHz,상위조성우우-103 dBc/Hz@1 kHz,각항지표만족실제공정요구。
The method of generating and implementing a kind of linear frequency modulation ( LFM ) radar signals with low phase noise is introduced. The 1 GHz PLL is designed as DDS’s clock driver circuit using HMC704 control VCO by analyzing the spectrum of the output signal and the DDS spurious. The loop filter and AD9910 hardware circuit is also optimized in order to improve the phase noise and spurious. The register parameters is calculated and SPI bus timing is analyzed,DDS and PLL is configured high-speedy by FPGA. Experimental results show that the LFM source output amplitude greater than -3 dBm,frequency step is 1 kHz,the phase noise is better than -103 dBc/Hz@1 kHz,the indicators meet the practical engineering requirements.