CAJ | 학술논문

比较器广泛应用于模拟信号到数字信号的转换过程中，在模-数转换过程中，对输入进行采样后的信号通过比较器以决定模拟信号的数字量。滞回比较器也叫迟滞比较器，以其优越的抗噪声能力在比较器中占有重要地位。描述一种滞回比较器，使用少量元件节省成本，滞回电压阈值设计灵活，同时用P管作差分输入管，有较高的共模输入范围，转换速率快。使用0.18μm CMOS工艺分别对转折点压差为200 mV的设计进行仿真，仿真结果与设计预期相符合。
비교기엄범응용우모의신호도수자신호적전환과정중，재모-수전환과정중，대수입진행채양후적신호통과비교기이결정모의신호적수자량。체회비교기야규지체비교기，이기우월적항조성능력재비교기중점유중요지위。묘술일충체회비교기，사용소량원건절성성본，체회전압역치설계령활，동시용P관작차분수입관，유교고적공모수입범위，전환속솔쾌。사용0.18μm CMOS공예분별대전절점압차위200 mV적설계진행방진，방진결과여설계예기상부합。
Comparator is widely used in conversion of analog signal to digital signal. In analog-to-digital conversion, the input signal is sampled by comparator to determined the output digital signal. Hysteresis comparator also called sluggish comparator with superior anti noise ability plays an important role in comparator. The paper describes a hysteresis comparator with simple structure and hysteresis voltage threshold design lfexibility. At the same time PMOS are the differential input transistors and the comparator has high common mode input range and large slew rate. The design with turning point of voltage difference 200 mV is simulated with 0.18 μm CMOS process and the results are accord with the desired outcome.