CAJ | 학술논문

共晶焊接装片以其稳定可靠的性能在微电子封装领域得到了越来越广泛的应用。在焊接过程中，由于界面氧化、沾污等原因产生的焊接层空洞对芯片的散热有较大的影响。研究了影响空洞率大小的因素，并采用有限元方法仿真分析了不同空洞对热阻的影响。根据仿真结果可以看出：空洞率在小于10%时，结壳热阻随着空洞率的增大没有显著的变化；当空洞率大于10%时，结壳热阻随着空洞率的增大而线性增加；当空洞率相同时，连续空洞的热阻几乎是分散空洞的热阻的两倍。实验结果表明利用等离子清洗机对焊接界面清洗能有效地降低焊接空洞率，芯片表面要有适当的压力来控制空洞率和焊接层厚度。
공정한접장편이기은정가고적성능재미전자봉장영역득도료월래월엄범적응용。재한접과정중，유우계면양화、첨오등원인산생적한접층공동대심편적산열유교대적영향。연구료영향공동솔대소적인소，병채용유한원방법방진분석료불동공동대열조적영향。근거방진결과가이간출：공동솔재소우10%시，결각열조수착공동솔적증대몰유현저적변화；당공동솔대우10%시，결각열조수착공동솔적증대이선성증가；당공동솔상동시，련속공동적열조궤호시분산공동적열조적량배。실험결과표명이용등리자청세궤대한접계면청세능유효지강저한접공동솔，심편표면요유괄당적압력래공제공동솔화한접층후도。
Eutectic welding is widely used in microelectronic package because of its high bonding strength and reliability. However, voids are easily formed in the solder layer during bonding process which attributed to oxide and contamination at the bonding interfaces, and have great influence on thermal performance of device. In the paper, Research is carried out to study the effect of void size and configuration on thermal resistance (θjc) by means of finite element analysis (FEA), and the influencing factor of void size. According to FEA results, it is obviously that theθjc is almost unchanged when the void ratio is less than 10%; but when the void ratio is more than 10%,θjc increases rapidly with the increase of void ratio, and in the condition of same void ratio,θjc of continuous void is nearly double that of scattered void. The results show that interface treated by microwave plasma cleaning has low void ratio, and proper pressure on the die is necessary to control the void ratio and thickness of bonding layer.