CAJ | 학술논문

延迟锁相环能够产生精确的延时而被广泛使用。本文介绍了一种适用于直接调制发射机锁相电路环路校准的延迟锁相环。电路采用TSMC 0.18μm CMOS工艺实现,参考频率为26 MHz。在3.3 V电源电压下的仿真结果显示：延迟锁相环锁定时间为520ns，锁定相位为2π，同时输出8路相位差为45o间隔的时钟。
연지쇄상배능구산생정학적연시이피엄범사용。본문개소료일충괄용우직접조제발사궤쇄상전로배로교준적연지쇄상배。전로채용TSMC 0.18μm CMOS공예실현,삼고빈솔위26 MHz。재3.3 V전원전압하적방진결과현시：연지쇄상배쇄정시간위520ns，쇄정상위위2π，동시수출8로상위차위45o간격적시종。
Delay locked loop is widely used because it may generate an accurate delay. This paper introduces a delay locked loop applied to loop calibration for PLL circuit of direct modulation transmitter. The whole circuit used TSMC 0.18μm CMOS technology with a reference frequency of 26 MHz. The power supply is 3.3V. The simulation results show that the circuit has a locking time of about 520ns and a locking phase of 2π. It also can output eight clocks with the same phase interval of 45o.