CAJ | 학술논문

针对动态电压/频率调整系统芯片中时钟同步问题,设计一个具有宽工作频率范围和固定锁定周期的快速锁定全数字逐次逼近延时锁定环,采用改进的可复位数字控制延时线方法,在减小面积和提高最高工作频率的同时,有效地解决传统全数字逐次逼近延时锁定环的谐波锁定和零延时陷阱问题。整个延时锁定环采用 TSMC-65 nm CMOS工艺标准单元库实现,仿真结果表明,在典型工艺角和25℃情况下,工作频率范围为250 MHz~2 GHz,锁定时间为固定的18个输入时钟周期,当电源电压为1.2 V、输入时钟频率为2 GHz时,功耗为0.4 mW。
침대동태전압/빈솔조정계통심편중시종동보문제,설계일개구유관공작빈솔범위화고정쇄정주기적쾌속쇄정전수자축차핍근연시쇄정배,채용개진적가복위수자공제연시선방법,재감소면적화제고최고공작빈솔적동시,유효지해결전통전수자축차핍근연시쇄정배적해파쇄정화령연시함정문제。정개연시쇄정배채용 TSMC-65 nm CMOS공예표준단원고실현,방진결과표명,재전형공예각화25℃정황하,공작빈솔범위위250 MHz~2 GHz,쇄정시간위고정적18개수입시종주기,당전원전압위1.2 V、수입시종빈솔위2 GHz시,공모위0.4 mW。
An all digital fast-locking Successive Approximation Register-controlled Delay-Locked Loop( SARDLL) with wide-range operating frequency and constant acquisition cycles is presented for the clock synchronization of Dynamic Voltage/Frequency Scaling ( DVFS ) System-on-Chip ( SoC ) . The improved resettable Digitally Controlled Delay Line ( DCDL) scheme is adopted to effectively solve the harmonic lock problem and zero-delay problem of the conventional all digital SARDLL,meanwhile reduces the hardware overhead and increases the maximum operating frequency. The presented all digital SARDLL is implemented using the TSMC-65 nm CMOS standard cell library. Based on the typical corner and 25℃,the post-layout simulation results show that the operating frequency range is from 250 MHz to 2 GHz,the lock time is 18 cycles of the input clock signal and the power consumption is 0. 4 mW at 2 GHz and 1. 2 V supply voltage.