CAJ | 학술논문

为了满足SoC系统对多种高速串行通信协议的兼容性要求，文中提出了一种最高支持3.125 Gbps的多协议统一架构Serdes发送器电路结构，并在0.13μm CMOS工艺下实现。该结构通过分频比可编程的PLL电路来产生不同频率的时钟信号，并通过差分电荷泵电路降低了的分频比可调地降低了PLL电路输出时钟信号的抖动；通过上升/下降时间控制电路来改变输出信号的上升/下降沿时间，并通过控制信号来改变驱动器的输出信号幅度以及预加重幅度，从而满足不同协议对输出信号的上升/下降时间以及输出幅度的要求。测试结果表明，该发送器电路输出信号眼图可以满足PCI-E、Fi-ber Channel、SRIO等协议的模板要求，在3.125 Gbps速率下，其随机抖动RJRMS为1.81 ps。
위료만족SoC계통대다충고속천행통신협의적겸용성요구，문중제출료일충최고지지3.125 Gbps적다협의통일가구Serdes발송기전로결구，병재0.13μm CMOS공예하실현。해결구통과분빈비가편정적PLL전로래산생불동빈솔적시종신호，병통과차분전하빙전로강저료적분빈비가조지강저료PLL전로수출시종신호적두동；통과상승/하강시간공제전로래개변수출신호적상승/하강연시간，병통과공제신호래개변구동기적수출신호폭도이급예가중폭도，종이만족불동협의대수출신호적상승/하강시간이급수출폭도적요구。측시결과표명，해발송기전로수출신호안도가이만족PCI-E、Fi-ber Channel、SRIO등협의적모판요구，재3.125 Gbps속솔하，기수궤두동RJRMS위1.81 ps。
In order to meet the compatibility requirements of SoC system for a variety of high speed serial communication protocol,pro-pose a multi protocol unified Serdes transmitter architecture which can support maximum 3. 125 Gbps and has been realized in a 0. 13 μm CMOS technology. The dividing ratio of PLL can be programmed to produce different frequency,and the jitter of the PLL output clock is reduced through differential charge pump circuit. This transmitter architecture uses rising/falling edge control circuit to change the rise/fall time of the output signal,and uses control signal to change the amplitude and pre-emphasis amplitude of the driver so as to meet the different protocols requirements. Measurement results show that the output of the transmitter can meet the eye diagram template of the PCI-E,Fiber Channel and SRIO,the random jitter of the transmitter is 1. 81 ps at the rate of 3. 125 Gbps.