CAJ | 학술논문

时钟恢复电路( CDR)是高速串行通讯中的重要模块,对通讯的稳定性和误码率有直接的影响,易受PVT影响。PCIE,RapidIO等高速串行通讯协议中又对CDR的性能指标分别有数据抖动特性及抖动容限的容忍范围等严格定义。由于单一协议和速率设计的CDR电路在电路应用、验证测试和集成的复杂度较大,多协议兼容是技术趋势。文中设计实现了一种多协议兼容的双环时钟恢复电路,采用集成自适应带宽的锁相环结构PI插相器,配合数字控制、相位插值的方式实现。经流片验证,在1~3.125 Gbps速率范围内抖动容限和频率偏移等指标均满足协议标准值要求,误码率小于1E-12,满足FC(FC-PI-4)、PCIE(1.1)和Rapid IO(1.3)的协议要求,工作温度范围为-55~125益。目前该电路已成功应用于PCIE、FC和RapidIO等多款SerDes中,并集成应用于多款高性能SoC芯片中。
시종회복전로( CDR)시고속천행통신중적중요모괴,대통신적은정성화오마솔유직접적영향,역수PVT영향。PCIE,RapidIO등고속천행통신협의중우대CDR적성능지표분별유수거두동특성급두동용한적용인범위등엄격정의。유우단일협의화속솔설계적CDR전로재전로응용、험증측시화집성적복잡도교대,다협의겸용시기술추세。문중설계실현료일충다협의겸용적쌍배시종회복전로,채용집성자괄응대관적쇄상배결구PI삽상기,배합수자공제、상위삽치적방식실현。경류편험증,재1~3.125 Gbps속솔범위내두동용한화빈솔편이등지표균만족협의표준치요구,오마솔소우1E-12,만족FC(FC-PI-4)、PCIE(1.1)화Rapid IO(1.3)적협의요구,공작온도범위위-55~125익。목전해전로이성공응용우PCIE、FC화RapidIO등다관SerDes중,병집성응용우다관고성능SoC심편중。
CDR is the important module of high speed serial communication,and has direct effect on stability and bit error rate of commu-nication,and accessible to PVT. PCIE,RapidIO and other high speed serial communication protocols have strict definitions of data jitter property and jitter tolerance. Due to the complexity of CDR circuit with single protocol and speed ratio design in circuit application,test and integration,multi-protocol compatibility is the trend. A multi-protocol dual-path CDR integrated adaptive bandwidth PLL is present in this paper. Use digital control and phase interpolation methods and adjust the CDR bandwidth by configuring digital control bits to re-cover the clock and data correctly at different rates. The measured results show that jitter tolerance and frequency deviation is met the pro-tocol standard value from 1 to 3. 125 Gbps,and the bit error rate is less than 1E-12,which are all met the requirements of protocol FC (FC-PI-4)、PCIE(1.1) andRapidIO(1.3),theoperatingtemperaturerangeis-55~125℃.Atpresent,thecircuithasbeenusedina variety of high speed SerDes chip successfully,and integrated in a variety of SoC with high performance.