CAJ | 학술논문

三输入AND/XOR门是Reed-Muller(RM)逻辑电路的一种基本复合门电路单元. 针对现有AND/XOR门电路由AND门和XOR/XNOR门级联而成, 导致电路延时长、功耗大等问题, 提出一种晶体管级的CMOS逻辑和传输逻辑混合的低功耗三输入AND/XOR门电路.首先在55nm CMOS工艺下,对所设计电路进行原理图和版图设计;然后对版图进行寄生参数提取, 并在不同工艺角下与基于典型级联结构的电路进行后仿真分析和比较. 实验结果表明,在典型工艺角下,所提出的电路的面积、功耗和功耗延迟积的改进最高分别达到18.79%, 26.67%与31.25%.
삼수입AND/XOR문시Reed-Muller(RM)라집전로적일충기본복합문전로단원. 침대현유AND/XOR문전로유AND문화XOR/XNOR문급련이성, 도치전로연시장、공모대등문제, 제출일충정체관급적CMOS라집화전수라집혼합적저공모삼수입AND/XOR문전로.수선재55nm CMOS공예하,대소설계전로진행원리도화판도설계;연후대판도진행기생삼수제취, 병재불동공예각하여기우전형급련결구적전로진행후방진분석화비교. 실험결과표명,재전형공예각하,소제출적전로적면적、공모화공모연지적적개진최고분별체도18.79%, 26.67%여31.25%.
3-input AND/XOR gate is the basic complex gate for Reed-Muller (RM) logic circuit implementation. To cope with the issues of the present AND and XOR cascaded AND/XOR gate with long delay time and high power, a transistor-level based low power 3-input AND/XOR gate, which is implemented with hybrid logic of CMOS logic and transmit logic, is proposed.First,under 55nm CMOS process, the circuit schematic is proposed and its layout is implemented. Then, the parasitic parameter extraction based on the circuit layout and the post-simulations under different process corners are carried out. Under typical process corners, the simulation results show that, the improvement of the proposed circuit can be up to 18.79%, 26.67% and 31.25% respectively in terms of the area, power and power delay product compared with the classical cascaded designs.