电脑知识与技术
電腦知識與技術
전뇌지식여기술
COMPUTER KNOWLEDGE AND TECHNOLOGY
2015年
11期
213-215
,共3页
串行器/解串器%锁相环%鉴频鉴相器%分频器%压控振荡器
串行器/解串器%鎖相環%鑒頻鑒相器%分頻器%壓控振盪器
천행기/해천기%쇄상배%감빈감상기%분빈기%압공진탕기
Serializer/Deserializer (SerDes)%PLL%PFD%Frequency divider%VCO
根据SerDes误码率的设计指标,基于65nm CMOS工艺设计实现了一种自适应带宽锁相环电路。分析了自适应锁相环的数学模型，给出了自适应带宽锁相环的简易设计方法。采用双电荷泵电路结构，极大地减小了芯片面积。该文的PLL采用1 V和2.5 V两种电源供电，输出时钟频率范围为400～2000 MHz，适用于0.8～4 Gbit/s传输速率的SerDes。样品电路测试表明，输出时钟频率为2GHz时，时钟均方根抖动为1.68ps，功耗为14mW，芯片面积为0.0704mm2。
根據SerDes誤碼率的設計指標,基于65nm CMOS工藝設計實現瞭一種自適應帶寬鎖相環電路。分析瞭自適應鎖相環的數學模型，給齣瞭自適應帶寬鎖相環的簡易設計方法。採用雙電荷泵電路結構，極大地減小瞭芯片麵積。該文的PLL採用1 V和2.5 V兩種電源供電，輸齣時鐘頻率範圍為400～2000 MHz，適用于0.8～4 Gbit/s傳輸速率的SerDes。樣品電路測試錶明，輸齣時鐘頻率為2GHz時，時鐘均方根抖動為1.68ps，功耗為14mW，芯片麵積為0.0704mm2。
근거SerDes오마솔적설계지표,기우65nm CMOS공예설계실현료일충자괄응대관쇄상배전로。분석료자괄응쇄상배적수학모형，급출료자괄응대관쇄상배적간역설계방법。채용쌍전하빙전로결구，겁대지감소료심편면적。해문적PLL채용1 V화2.5 V량충전원공전，수출시종빈솔범위위400～2000 MHz，괄용우0.8～4 Gbit/s전수속솔적SerDes。양품전로측시표명，수출시종빈솔위2GHz시，시종균방근두동위1.68ps，공모위14mW，심편면적위0.0704mm2。
A low power phase-locked loop with adaptive bandwidth was based on the design specification of SerDes and designed based on 65 nm CMOS (Complementary Metal Oxide Semiconductor, CMOS) process was presented. The adaptive bandwidth theo?ry of PLL is analyzed and an easy method for adaptive bandwidth was proposed. The chip area was minimized by using the pro?posed architecture based on dual charge pump circuit architecture. The PLL had an output frequency range from 400 MHz to 2 GHz at 1 V and 2.5 V supply voltage, the PLL can be used as a clock for SerDes at speed from 800 Mbit/s to 4 Gbit/s. And the test results showed that, 1.68ps RMS jitter at 2 GHz output frequency, the circuit occupied a chip area of 0.0704 mm2 and consumed 14mW power.
