电机与控制学报
電機與控製學報
전궤여공제학보
ECTRIC MACHINES AND CONTROL
2015年
5期
58-66
,共9页
吴瑕杰%方辉%宋文胜%冯晓云
吳瑕傑%方輝%宋文勝%馮曉雲
오하걸%방휘%송문성%풍효운
辅助逆变器%空间矢量脉宽调制%三电平%DSP%FPGA
輔助逆變器%空間矢量脈寬調製%三電平%DSP%FPGA
보조역변기%공간시량맥관조제%삼전평%DSP%FPGA
auxiliary inverter%pace vector pulse width modulation%hree-level%DSP%PGA
辅助逆变器为电力机车辅助设备供电,其性能将直接影响电力机车的整体运行情况。本文所述辅助逆变器核心控制系统采用基于浮点数字信号处理器( digital signal processor, DSP)和现场可编程门阵列( field programmable gate array, FPGA)的系统架构。以FPGA部分为重点,采用了一种基于矢量旋转的简化三电平空间矢量脉宽调制( space vector pulse width modulation, SVPWM),并通过三角函数运算的简化、高效率除法器等关键性设计避免DSP进行大量三角函数运算,减少硬件资源占用。实现了基于FPGA的AD采样与数据处理及DSP与FPGA之间基于双端口RAM的异步通信,充分利用了FPGA强大的高速并行处理能力。最后,搭建基于RT-LAB与辅助逆变器核心控制系统的半实物实验平台,实验结果证明了辅助逆变器核心控制系统FPGA部分设计方案的可行性与正确性。
輔助逆變器為電力機車輔助設備供電,其性能將直接影響電力機車的整體運行情況。本文所述輔助逆變器覈心控製繫統採用基于浮點數字信號處理器( digital signal processor, DSP)和現場可編程門陣列( field programmable gate array, FPGA)的繫統架構。以FPGA部分為重點,採用瞭一種基于矢量鏇轉的簡化三電平空間矢量脈寬調製( space vector pulse width modulation, SVPWM),併通過三角函數運算的簡化、高效率除法器等關鍵性設計避免DSP進行大量三角函數運算,減少硬件資源佔用。實現瞭基于FPGA的AD採樣與數據處理及DSP與FPGA之間基于雙耑口RAM的異步通信,充分利用瞭FPGA彊大的高速併行處理能力。最後,搭建基于RT-LAB與輔助逆變器覈心控製繫統的半實物實驗平檯,實驗結果證明瞭輔助逆變器覈心控製繫統FPGA部分設計方案的可行性與正確性。
보조역변기위전력궤차보조설비공전,기성능장직접영향전력궤차적정체운행정황。본문소술보조역변기핵심공제계통채용기우부점수자신호처리기( digital signal processor, DSP)화현장가편정문진렬( field programmable gate array, FPGA)적계통가구。이FPGA부분위중점,채용료일충기우시량선전적간화삼전평공간시량맥관조제( space vector pulse width modulation, SVPWM),병통과삼각함수운산적간화、고효솔제법기등관건성설계피면DSP진행대량삼각함수운산,감소경건자원점용。실현료기우FPGA적AD채양여수거처리급DSP여FPGA지간기우쌍단구RAM적이보통신,충분이용료FPGA강대적고속병행처리능력。최후,탑건기우RT-LAB여보조역변기핵심공제계통적반실물실험평태,실험결과증명료보조역변기핵심공제계통FPGA부분설계방안적가행성여정학성。
Auxiliary inverter is used to power supply electric locomotive auxiliary devices and its operation performance affects the operation of electric locomotive directly. A new system structure based on DSP and FPGA was adopted to the auxiliary inverter core control system. A simplified three-level space vector pulse width modulation( SVPWM) algorithm which can relieve digital signal processor ( DSP/MCU) from heavy computation task through the simplified design of multiplier and divider units was adopted to the auxiliary inverter core control system. In order to make full use of high-speed parallel processing ability of FPGA, implementation scheme of AD capture and data processing, asynchronous communication between DSP and FPGA based on dual-port RAM were proposed in this paper. Finally, accuracy and feasibility of FPGA part in the auxiliary inverter core control system were verified by hardware-in-loop experimental platform based on RT-LAB and the auxiliary inverter core control system.