CAJ | 학술논문

介绍了采用65 nm工艺实现宽频带和低相位噪声LC－VCO。利用相邻两层金属以及多层金属之间的寄生电容来实现堆积式MOM电容。开关阵列电容采用所述的堆积电容来实现，在实现宽频带调谐的基础上可减小VCO的调谐增益。在交叉耦合MOS管的漏极插入电阻来抑制有源器件中闪烁噪声，这种非谐振方式可保证闪烁噪声的抑制在宽频带范围内有效。压控振荡器采用65 nm CMOS工艺实现，测试得到的调谐频率范围为2．7 GHz 1．3 GHz；输出频率为1．3 GHz时的相位噪声为－124 dBc／Hz＠1 MHz；供电电压为1．2 V时，功耗为2．4 mW；相应的优值为－183 dBc／Hz。
개소료채용65 nm공예실현관빈대화저상위조성LC－VCO。이용상린량층금속이급다층금속지간적기생전용래실현퇴적식MOM전용。개관진렬전용채용소술적퇴적전용래실현，재실현관빈대조해적기출상가감소VCO적조해증익。재교차우합MOS관적루겁삽입전조래억제유원기건중섬삭조성，저충비해진방식가보증섬삭조성적억제재관빈대범위내유효。압공진탕기채용65 nm CMOS공예실현，측시득도적조해빈솔범위위2．7 GHz 1．3 GHz；수출빈솔위1．3 GHz시적상위조성위－124 dBc／Hz＠1 MHz；공전전압위1．2 V시，공모위2．4 mW；상응적우치위－183 dBc／Hz。
A wideband low phase noise LC-VCO implemented in 65 nm CMOS process was presented .By using the parasitic capacitance between the adjacent metal layers and the multi-layers of metals, a stacked MOM-capacitor is formed .The switched array composed of the proposed capacitor is introduced to keep small VCO-gain while achieve large tuning range of the LC-VCO.A resistor is inserted in series with the drain of the cross-coupled FET to suppress the flicker noise up-conversion of active devices .The non-resonant method allows flicker noise up-conversion suppression over a wideband frequency range .The proposed LC-VCO was implemented in 65 nm CMOS process , the measured frequency range is from 2.7 GHz to 1.3 GHz, resulting a tuning range of 70%.The measured phase noise is -124 dBc/Hz@1 MHz at 1.3 GHz output .The power dissipation is 2.4 mW under 1.2 V supply voltage , the corresponding FOM is -183 dBc/Hz.