CAJ | 학술논문

设计了一个2 GHz全集成的CMOS功率放大器（PA），该PA的匹配网络采用片上变压器实现，片上变压器用来实现单端信号和差分信号之间的转换和输入、输出端的阻抗匹配。采用ADS Momentum软件对片上变压器进行电磁仿真，在2 GHz频点，输入、级间和输出变压器的功率传输效率分别为74.2%，75.5%和78.4%。该PA基于TSMC 65 nm CMOS模型设计，采用Agilent ADS软件进行电路仿真，仿真结果表明：在2.5 V供电电压、2 GHz工作频率点，PA的输入、输出完全匹配到50?（S11=–22.4 dB、S22=–13.5 dB），功率增益为33.2 dB，最高输出功率达到23.4 dBm，最高功率附加效率（PAE）达到35.3%，芯片面积仅为1.01 mm2。
설계료일개2 GHz전집성적CMOS공솔방대기（PA），해PA적필배망락채용편상변압기실현，편상변압기용래실현단단신호화차분신호지간적전환화수입、수출단적조항필배。채용ADS Momentum연건대편상변압기진행전자방진，재2 GHz빈점，수입、급간화수출변압기적공솔전수효솔분별위74.2%，75.5%화78.4%。해PA기우TSMC 65 nm CMOS모형설계，채용Agilent ADS연건진행전로방진，방진결과표명：재2.5 V공전전압、2 GHz공작빈솔점，PA적수입、수출완전필배도50?（S11=–22.4 dB、S22=–13.5 dB），공솔증익위33.2 dB，최고수출공솔체도23.4 dBm，최고공솔부가효솔（PAE）체도35.3%，심편면적부위1.01 mm2。
A fully integrated CMOS power amplifier (PA) operating at 2 GHz was designed, with on-chip transformers-based match networks used to realize the conversion of single-end between differential signals and the impedance match of input and output port. On-chip transformer was simulated using electromagnetic simulator ADS Momentum, and the efficiencies of input match, inter-stage and output match networks were 74.2%, 75.5% and 78.4%, respectively. The PA was designed and simulated in Agilent’s ADS using TSMC 65 nm CMOS spice model. According to the simulation results of PA operating at 2 GHz and supplied 2.5 V, input and output impedances are fully matched to 50?(S11 = –22.4 dB,S22= –13.5 dB), power gain is 33.2 dB, the saturated output power is 23.4 dBm, the maximum PAE is 35.3%, and the chip’s area is only 1.01 mm2.