电子科技大学学报
電子科技大學學報
전자과기대학학보
JOURNAL OF UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
2015年
3期
428-432
,共5页
胡伟%慕德俊%黄兴利%邰瑜
鬍偉%慕德俊%黃興利%邰瑜
호위%모덕준%황흥리%태유
隐通道%门级信息流分析%信息流控制%安全体系架构%安全漏洞
隱通道%門級信息流分析%信息流控製%安全體繫架構%安全漏洞
은통도%문급신식류분석%신식류공제%안전체계가구%안전루동
covert channel%gate level information flow analysis%information flow control%secure architecture%security vulnerability
现代处理器架构中的缓存器、分支预测器等部件通常都包含难以检测的隐通道,成为攻击者入侵系统的切入点。现有方法难以有效地检测硬件相关的隐通道,从而使得这些安全漏洞往往在攻击造成严重损失后才暴露出来。该文构建了一种基于执行租赁机制的安全体系架构,以严格控制不可信执行环境的影响边界,保证不同执行环境之间的严格隔离,并采用门级抽象层次上的信息流分析方法,建立硬件架构的信息流模型,实现对硬件中全部逻辑信息流的精确度量,通过捕捉有害信息流动来检测硬件架构中潜在的安全漏洞,进而通过指令集架构的信息流模型向上层提供信息流度量能力,以实现软硬件联合安全验证。
現代處理器架構中的緩存器、分支預測器等部件通常都包含難以檢測的隱通道,成為攻擊者入侵繫統的切入點。現有方法難以有效地檢測硬件相關的隱通道,從而使得這些安全漏洞往往在攻擊造成嚴重損失後纔暴露齣來。該文構建瞭一種基于執行租賃機製的安全體繫架構,以嚴格控製不可信執行環境的影響邊界,保證不同執行環境之間的嚴格隔離,併採用門級抽象層次上的信息流分析方法,建立硬件架構的信息流模型,實現對硬件中全部邏輯信息流的精確度量,通過捕捉有害信息流動來檢測硬件架構中潛在的安全漏洞,進而通過指令集架構的信息流模型嚮上層提供信息流度量能力,以實現軟硬件聯閤安全驗證。
현대처리기가구중적완존기、분지예측기등부건통상도포함난이검측적은통도,성위공격자입침계통적절입점。현유방법난이유효지검측경건상관적은통도,종이사득저사안전루동왕왕재공격조성엄중손실후재폭로출래。해문구건료일충기우집행조임궤제적안전체계가구,이엄격공제불가신집행배경적영향변계,보증불동집행배경지간적엄격격리,병채용문급추상층차상적신식류분석방법,건립경건가구적신식류모형,실현대경건중전부라집신식류적정학도량,통과포착유해신식류동래검측경건가구중잠재적안전루동,진이통과지령집가구적신식류모형향상층제공신식류도량능력,이실현연경건연합안전험증。
Components such as caches and branch predictors in modern processor architectures tend to include hard-to-detect covert channels, which provide a foot-holder for attackers to perform malicious activities. However, existing methods are inefficient in detecting hardware-specific covert channels. As a consequence, these security holes expose only after significant damages are inflicted. In this paper, a secure architecture based on the execution lease mechanism is built in order to tightly bound the effects of untrusted execution contexts and enforce the strict isolation of execution contexts. Further, the information flow model of the hardware architecture is constructed by using the gate level information flow analysis method, which allows the precise measurement of all digital flows in the underlying hardware and the detection of security vulnerabilities by capturing harmful flows of information. In addition, hardware/software security co-verification can be achieved with the aid of information flow measurement capability provided by the information flow model of the instruction set architecture.