CAJ | 학술논문

为了进一步提高集成电路互连寄生参数提取和电路时延分析的准确性，实现基于准确场求解器的线网寄生参数提取，提出一种快速、准确的集成电路版图数据转换方法。该方法读入二维GDSII版图数据和垂直工艺信息，基于一种扫描线算法判断导体块之间是否连接或重叠；然后利用链表、并查集等数据结构有效地描述三维互连结构及导体间连通关系，为后续电容提取和互连时延分析提供必要信息；最后输出电容提取场求解器所需的三维互连结构数据。基于实际版图的实验结果表明，文中方法比基于多边形两两判断的算法快4～7倍，且加速比随处理版图规模的增大而增大；该方法整体上具有O(nlog n)的时间复杂度，其中n为导体块数目，能够快速处理含1万块以上导体的大规模集成电路设计版图。
위료진일보제고집성전로호련기생삼수제취화전로시연분석적준학성，실현기우준학장구해기적선망기생삼수제취，제출일충쾌속、준학적집성전로판도수거전환방법。해방법독입이유GDSII판도수거화수직공예신식，기우일충소묘선산법판단도체괴지간시부련접혹중첩；연후이용련표、병사집등수거결구유효지묘술삼유호련결구급도체간련통관계，위후속전용제취화호련시연분석제공필요신식；최후수출전용제취장구해기소수적삼유호련결구수거。기우실제판도적실험결과표명，문중방법비기우다변형량량판단적산법쾌4～7배，차가속비수처리판도규모적증대이증대；해방법정체상구유O(nlog n)적시간복잡도，기중n위도체괴수목，능구쾌속처리함1만괴이상도체적대규모집성전로설계판도。
In order to improve the accuracy of parasitic extraction and timing analysis of integrated circuits (ICs), and perform the capacitance extraction with three-dimensional (3D) field solver, a fast transformation method is proposed to convert IC layout data. The method reads in GDSII file and vertical technology information, and then determines whether conductor blocks are connected or overlapped based on a sweep line algorithm. After that, the data structures of list and union-find set are used to describe the interconnect blocks and the connectivity among them, which is necessary for the subsequent capacitance extraction and timing analysis. Finally, the method out-puts the 3D structure data for capacitance extraction field solver. The experimental results based on actual layouts show that, the proposed method is 4X~7X faster than the method based on pairwise analysis, and the speedup ra-tio increases as the number of blocks in the design increases. The time complexity of the proposed method is O(nlog n), wheren is the number of blocks in the design layout. Therefore, the method is able to handle actual circuit layout with more than 10,000 blocks efficiently.