液晶与显示
液晶與顯示
액정여현시
CHINESE JOURNAL OF LIQUID CRYSTALS AND DISPLAYS
2015年
3期
432-436
,共5页
白金超%王玉堂%郭总杰%丁向前%袁剑峰%邵喜斌
白金超%王玉堂%郭總傑%丁嚮前%袁劍峰%邵喜斌
백금초%왕옥당%곽총걸%정향전%원검봉%소희빈
薄膜晶体管阵列工艺%接触电阻%过孔设计优化
薄膜晶體管陣列工藝%接觸電阻%過孔設計優化
박막정체관진렬공예%접촉전조%과공설계우화
thin film transistor array process%contact resistance%via hole design optimization
研究了过孔接触电阻变化规律,并进行机理分析,为优化薄膜晶体管的过孔设计提供依据。首先,运用开尔文四线检测法对不同大小、形状、数量的钼/铝/钼结构的栅极和源/漏层金属与氧化铟锡连接过孔的接触电阻进行测试。然后,通过扫描电子显徽镜、能量色散 X射线光谱仪和聚焦离子束显徽镜对过孔内部形貌进行表征。最后,对过孔接触电阻变化规律进行机理分析。实验结果表明:过孔面积越大,接触电阻越小;过孔面积相同时,长方形过孔的接触电阻小于正方形过孔的接触电阻,多小孔的接触电阻小于单大孔的接触电阻,栅极金属与氧化铟锡的过孔接触电阻小于源/漏层金属与氧化铟锡的过孔接触电阻。为了降低钼/铝/钼与氧化铟锡连接过孔的接触电阻,过孔面积尽可能最大化,采用长方形过孔优于正方形过孔,多小过孔优于单大孔设计,同时优化过孔刻蚀工艺,减少过孔内顶层钼的损失。
研究瞭過孔接觸電阻變化規律,併進行機理分析,為優化薄膜晶體管的過孔設計提供依據。首先,運用開爾文四線檢測法對不同大小、形狀、數量的鉬/鋁/鉬結構的柵極和源/漏層金屬與氧化銦錫連接過孔的接觸電阻進行測試。然後,通過掃描電子顯徽鏡、能量色散 X射線光譜儀和聚焦離子束顯徽鏡對過孔內部形貌進行錶徵。最後,對過孔接觸電阻變化規律進行機理分析。實驗結果錶明:過孔麵積越大,接觸電阻越小;過孔麵積相同時,長方形過孔的接觸電阻小于正方形過孔的接觸電阻,多小孔的接觸電阻小于單大孔的接觸電阻,柵極金屬與氧化銦錫的過孔接觸電阻小于源/漏層金屬與氧化銦錫的過孔接觸電阻。為瞭降低鉬/鋁/鉬與氧化銦錫連接過孔的接觸電阻,過孔麵積儘可能最大化,採用長方形過孔優于正方形過孔,多小過孔優于單大孔設計,同時優化過孔刻蝕工藝,減少過孔內頂層鉬的損失。
연구료과공접촉전조변화규률,병진행궤리분석,위우화박막정체관적과공설계제공의거。수선,운용개이문사선검측법대불동대소、형상、수량적목/려/목결구적책겁화원/루층금속여양화인석련접과공적접촉전조진행측시。연후,통과소묘전자현휘경、능량색산 X사선광보의화취초리자속현휘경대과공내부형모진행표정。최후,대과공접촉전조변화규률진행궤리분석。실험결과표명:과공면적월대,접촉전조월소;과공면적상동시,장방형과공적접촉전조소우정방형과공적접촉전조,다소공적접촉전조소우단대공적접촉전조,책겁금속여양화인석적과공접촉전조소우원/루층금속여양화인석적과공접촉전조。위료강저목/려/목여양화인석련접과공적접촉전조,과공면적진가능최대화,채용장방형과공우우정방형과공,다소과공우우단대공설계,동시우화과공각식공예,감소과공내정층목적손실。
In order to optimize via hole design of TFT array substrate and reduce via hole contact re-sistance,the contact resistance of different size,shape,number of Mo/Al/Mo and Indium-Tin Oxide (ITO)connection via holes are tested by Kelvin Four-terminal sensing.Then via hole morphology is characterized by scanning electron microscopy (SEM),focused ion beam (FIB)and energy dispersive spectroscopy (EDS).Finally,the mechanism of via hole contact resistance test results are analyzed. Experimental results indicate that the bigger via hole area is,the smaller the contact resistance will be,and in the same via hole area,the contact resistance of rectangular via hole is smaller than that of a square via hole,the contact resistance of the multi small holes is smaller than that of the single big via hole,the via hole contact resistance of Gate metal and ITO is smaller than that of SD metal and ITO.For reducing via hole contact resistance,via hole area is maximized.The rectangular via hole is better than that of the square via hole,the multi small holes are better than that of the single big via hole,and via etch process is optimized to reduce top Mo loss.