应用科技
應用科技
응용과기
YING YONG KE JI
2015年
3期
1-6
,共6页
信号处理%高速CMOS传感器%DDR2 SDRAM%信号完整性%反射串扰
信號處理%高速CMOS傳感器%DDR2 SDRAM%信號完整性%反射串擾
신호처리%고속CMOS전감기%DDR2 SDRAM%신호완정성%반사천우
signal processing%high speed CMOS detector%DDR2 SDRAM%signal integrity%reflection and crosstalk
基于CMV2000高速大面阵探测器构建了图像处理系统，为了在100 fps帧率的情况下同时采集和处理2片2 K×1 K面阵的图像，系统必须拥有足够的带宽缓存数据。采用Xilinx公司Virtex5系列FPGA作为主控器件，4片数据速率为533 Mbit／s的DDR2 SDRAM作为缓存设备，实现数据的采集、缓存和处理。高速并行的DDR2 SDRAM数据线的信号完整性将成为系统设计的薄弱环节，因此在电路硬件实际投入制造之前进行仿真是十分必要的。采用Cadence公司的SigXplore和SigNoise仿真工具对系统中DDR2 SDRAM的数据线进行了反射和串扰的仿真，得出了使用片上终端匹配（ ODT）和数控阻抗（ DCI）技术进行阻抗匹配时数据线的反射引起的信号上冲和下冲都在器件要求的范围之内，数据线在8 mil线宽8 mil间距2000 mil耦合距离的情况下串扰噪声在信号的噪声容限之内等结论。研究了高带宽的高速大面阵图像系统信号完整性仿真方法，仿真结果能够满足系统要求，从而为解决此类问题提供了思路和途径。
基于CMV2000高速大麵陣探測器構建瞭圖像處理繫統，為瞭在100 fps幀率的情況下同時採集和處理2片2 K×1 K麵陣的圖像，繫統必鬚擁有足夠的帶寬緩存數據。採用Xilinx公司Virtex5繫列FPGA作為主控器件，4片數據速率為533 Mbit／s的DDR2 SDRAM作為緩存設備，實現數據的採集、緩存和處理。高速併行的DDR2 SDRAM數據線的信號完整性將成為繫統設計的薄弱環節，因此在電路硬件實際投入製造之前進行倣真是十分必要的。採用Cadence公司的SigXplore和SigNoise倣真工具對繫統中DDR2 SDRAM的數據線進行瞭反射和串擾的倣真，得齣瞭使用片上終耑匹配（ ODT）和數控阻抗（ DCI）技術進行阻抗匹配時數據線的反射引起的信號上遲和下遲都在器件要求的範圍之內，數據線在8 mil線寬8 mil間距2000 mil耦閤距離的情況下串擾譟聲在信號的譟聲容限之內等結論。研究瞭高帶寬的高速大麵陣圖像繫統信號完整性倣真方法，倣真結果能夠滿足繫統要求，從而為解決此類問題提供瞭思路和途徑。
기우CMV2000고속대면진탐측기구건료도상처리계통，위료재100 fps정솔적정황하동시채집화처리2편2 K×1 K면진적도상，계통필수옹유족구적대관완존수거。채용Xilinx공사Virtex5계렬FPGA작위주공기건，4편수거속솔위533 Mbit／s적DDR2 SDRAM작위완존설비，실현수거적채집、완존화처리。고속병행적DDR2 SDRAM수거선적신호완정성장성위계통설계적박약배절，인차재전로경건실제투입제조지전진행방진시십분필요적。채용Cadence공사적SigXplore화SigNoise방진공구대계통중DDR2 SDRAM적수거선진행료반사화천우적방진，득출료사용편상종단필배（ ODT）화수공조항（ DCI）기술진행조항필배시수거선적반사인기적신호상충화하충도재기건요구적범위지내，수거선재8 mil선관8 mil간거2000 mil우합거리적정황하천우조성재신호적조성용한지내등결론。연구료고대관적고속대면진도상계통신호완정성방진방법，방진결과능구만족계통요구，종이위해결차류문제제공료사로화도경。
The image processing system described here is based on the high speed and large array detector CMV2000. In order to simultaneously collect and process two pieces of 2 K×1 K array image in the rate of 100 fps, the bandwidth must be wide enough for cache data. In this project, Xilinx Corporation Virtex5 series FPGA is used as the main controller, four pieces of 533 Mbit/s DDR2 SDRAM as the buffer to realize data acquisition, caching and processing. The signal integrity of parallel and high speed data lines of the DDR2 SDRAM then becomes the weak link of the system design;therefore it is necessary to perform simulation before the actual investment in circuit board manufacturing. This project uses the SigXplore and Signoise simulation tools of Cadence Corporation to simu?late the reflection and crosstalk of data lines of DDR2 SDRAM. The results show that with on?die termination ( ODT) and digital control impedance ( DCI) technology, the overshoot and undershoot caused by reflection of the data lines are both within the scope of the requirements, and the crosstalk noise of data lines in the condition of 8 mil spacing, 8mil linewidth and 2 000 mil coupling distance is within the noise tolerance. The signal integrity simu?lation method of the high bandwidth, high speed, large array image system is studied, and the simulation results can satisfy the system requirements, which provide the idea and way to solve this kind of problems.
