电子信息对抗技术
電子信息對抗技術
전자신식대항기술
ELECTRONIC INFORMATION WARFARE TECHNOLOGY
2015年
3期
72-75
,共4页
并行处理%延时最小均方算法%数据吞吐率%现场可编程门阵列
併行處理%延時最小均方算法%數據吞吐率%現場可編程門陣列
병행처리%연시최소균방산법%수거탄토솔%현장가편정문진렬
parallel processing%DLMS%data throughput%FPGA
通过将并行处理方法引入延时 LMS ( DLMS )算法,研究了一种新的并行延时 LMS (PDLMS)算法的FPGA实现。与DLMS算法相比,PDLMS算法具有更小的延时,更高的数据吞吐率,更快的收敛速度。使用Verilog HDL语言完成了该算法在硬件上的实现,同时给出了仿真结构,仿真验证了PDLMS算法比DLMS算法在性能上更具优越性。
通過將併行處理方法引入延時 LMS ( DLMS )算法,研究瞭一種新的併行延時 LMS (PDLMS)算法的FPGA實現。與DLMS算法相比,PDLMS算法具有更小的延時,更高的數據吞吐率,更快的收斂速度。使用Verilog HDL語言完成瞭該算法在硬件上的實現,同時給齣瞭倣真結構,倣真驗證瞭PDLMS算法比DLMS算法在性能上更具優越性。
통과장병행처리방법인입연시 LMS ( DLMS )산법,연구료일충신적병행연시 LMS (PDLMS)산법적FPGA실현。여DLMS산법상비,PDLMS산법구유경소적연시,경고적수거탄토솔,경쾌적수렴속도。사용Verilog HDL어언완성료해산법재경건상적실현,동시급출료방진결구,방진험증료PDLMS산법비DLMS산법재성능상경구우월성。
By introducing the parallel processing method into the delayed least mean square ( DLMS) algorithm, the FPGA implementation of a novel parallel processing method is studied. Compared with the DLMS algorithm, the parallel delayed least mean square ( PDLMS) algorithm has less time delay, the faster data throughput and higher convergence rate. The hardware im-plementation of PDLMS is achieved through hardware description language Verilog HDL and the simulation structure is also presented. The simulation results indicate that the PDLMS algorithm has certain performance advantages compared to DLMS.
