合肥工业大学学报（自然科学版）
閤肥工業大學學報（自然科學版）
합비공업대학학보（자연과학판）
JOURNAL OF HEFEI UNIVERSITY OF TECHNOLOGY(NATURAL SCIENCE)
2015年
6期
778-782,864
,共6页
ARM%时钟信号%信号上升时间%信号完整性%Allegro PCB SI软件
ARM%時鐘信號%信號上升時間%信號完整性%Allegro PCB SI軟件
ARM%시종신호%신호상승시간%신호완정성%Allegro PCB SI연건
ARM%clock signal%signal rise time%signal integrity(SI)%Allegro PCB SI software
高密度PCB（printed circuit board）设计中，高速时钟信号的信号完整性设计面临越来越大的挑战。针对该问题，文章研究了传输线的特性阻抗及其对信号传输延时的影响，利用Cadence的信号完整性分析软件Allegro PCB SI ，对一款基于ARM的嵌入式运动控制平台的时钟信号存在的信号完整性（signal integrity ，SI）问题进行了再现仿真，重点分析了信号反射与串扰现象及其产生原因，提出了减小时钟信号串扰和反射的措施；结合阻抗匹配原则，以嵌入式运动控制平台的SDRAM 和USB时钟信号为例，利用Allegro PCB SI对并行端接、串行端接、改变线间距等方法进行了试验，试验结果表明，端接匹配的方法能有效地减小时钟信号的反射和串扰现象。
高密度PCB（printed circuit board）設計中，高速時鐘信號的信號完整性設計麵臨越來越大的挑戰。針對該問題，文章研究瞭傳輸線的特性阻抗及其對信號傳輸延時的影響，利用Cadence的信號完整性分析軟件Allegro PCB SI ，對一款基于ARM的嵌入式運動控製平檯的時鐘信號存在的信號完整性（signal integrity ，SI）問題進行瞭再現倣真，重點分析瞭信號反射與串擾現象及其產生原因，提齣瞭減小時鐘信號串擾和反射的措施；結閤阻抗匹配原則，以嵌入式運動控製平檯的SDRAM 和USB時鐘信號為例，利用Allegro PCB SI對併行耑接、串行耑接、改變線間距等方法進行瞭試驗，試驗結果錶明，耑接匹配的方法能有效地減小時鐘信號的反射和串擾現象。
고밀도PCB（printed circuit board）설계중，고속시종신호적신호완정성설계면림월래월대적도전。침대해문제，문장연구료전수선적특성조항급기대신호전수연시적영향，이용Cadence적신호완정성분석연건Allegro PCB SI ，대일관기우ARM적감입식운동공제평태적시종신호존재적신호완정성（signal integrity ，SI）문제진행료재현방진，중점분석료신호반사여천우현상급기산생원인，제출료감소시종신호천우화반사적조시；결합조항필배원칙，이감입식운동공제평태적SDRAM 화USB시종신호위례，이용Allegro PCB SI대병행단접、천행단접、개변선간거등방법진행료시험，시험결과표명，단접필배적방법능유효지감소시종신호적반사화천우현상。
High‐speed clock signal has been faced up with more and more difficult challenges in high‐density printed circuit board (PCB) design .To solve this problem ,the impedance characteristic of transmission line and its impact on the signal propagation delay were studied ,the signal integrity(SI) problems of an embedded motion control platform based on ARM were simulated by using Allegro PCB SI which was an SI analysis tool of Cadence .The causes of signal reflections and crosstalk phe‐nomena were studied ,and then the measures to reduce these phenomena were proposed .Based on the impedance matching principle ,the methods of parallel termination ,serial termination ,changing line spacing were simulated and verified on USB clock signal and SDRAM clock signal by Allegro PCB SI . T he experimental results show that the termination matching method can effectively reduce the reflec‐tions and crosstalk phenomena of the clock signal .
