CAJ | 학술논문

设计了一款5-bit 4 GS/s的电阻插值型模数转换器（ADC），由预放大器阵列、高速比较器和编码器模块组成。定量分析了预放大器阵列的带宽和增益对ADC性能的影响，选取了最优的预放大器阵列结构，采样保持电路则选择了分布式采样，并采用电流逻辑模（CML）的比较器和编码电路。基于TSMC 65 nm工艺下进行仿真：在4 GHz的采样频率下，输入信号为200 MHz时，有效位数（ENOB）为4.85，SNDR为30.97，系统功耗为85 mW。
설계료일관5-bit 4 GS/s적전조삽치형모수전환기（ADC），유예방대기진렬、고속비교기화편마기모괴조성。정량분석료예방대기진렬적대관화증익대ADC성능적영향，선취료최우적예방대기진렬결구，채양보지전로칙선택료분포식채양，병채용전류라집모（CML）적비교기화편마전로。기우TSMC 65 nm공예하진행방진：재4 GHz적채양빈솔하，수입신호위200 MHz시，유효위수（ENOB）위4.85，SNDR위30.97，계통공모위85 mW。
A 5-bit 4 GS/s interpolation ADC was designed in the paper, which was composed of a pre-amplifier array, a high-speed comparator and an encoder module. The paper mathematically analyzed the impact of pre-amplifiers' bandwidth and gain on ADC performance and chose the optimum architecture of pre-amps array. Distributed S/H circuit, current-mode logic (CML) comparator banks and CML encoder were implemented. Based on TSMC 65 nm CMOS technology, this ADC was realized and simulated, reaching an ENOB of 4.85 bit, an SNDR of 30.97 and a power consumption of 85 mW at sampling rate of 4 GS/s and input signal of 200 MHz.