CAJ | 학술논문

针对在FPGA内部产生高速m序列时，处理时钟频率远低于数据生成速率的问题，采用延迟法、等效法和代换法3种方式，设计了并行m序列产生的并行结构，并在FPGA上进行了实现。经过测试，生成的并行m序列完全符合标准格式要求。这种并行结构在高速通信系统中的加解扰、误码测试和编译码测试等环节取得了较好的应用效果。
침대재FPGA내부산생고속m서렬시，처리시종빈솔원저우수거생성속솔적문제，채용연지법、등효법화대환법3충방식，설계료병행m서렬산생적병행결구，병재FPGA상진행료실현。경과측시，생성적병행m서렬완전부합표준격식요구。저충병행결구재고속통신계통중적가해우、오마측시화편역마측시등배절취득료교호적응용효과。
To resolve the problem of processing clock frequency far below data generation rate in generating high?speed m sequence in FPGA,this paper adopts three methods of delay method,equivalent method and substitution method to design the parallel structure for generating paralleling m sequence and implements it on FPGA. The test results show that the generated paralleling m sequences fully meet the standard format requirements.This parallel structure achieves better application effects in the tests of scrambling and descrambling,BER,and coding and decoding in high?speed communication system.