电子测量技术
電子測量技術
전자측량기술
ELECTRONIC MEASUREMENT TECHNOLOGY
2015年
7期
11-14
,共4页
动态部分重构%自重构%定制 IP核
動態部分重構%自重構%定製 IP覈
동태부분중구%자중구%정제 IP핵
dynamic partial reconfiguration%self-reconfiguration%custom-made IPs
基于EAPR(early access partial reconfiguration)动态部分重构(dynamic partial reconfiguration,DPR)方法,研究了在 FPGA上实现自重构嵌入式系统的设计方法。该方法运用 Xilinx的 ISE12.4开发工具,调用已有 IP 核,搭建包含用户定制IP核的自重构嵌入式系统硬件平台,并在Virtex5 FPGA上验证。设计中运用了二维重构技术,划分了3个可重构区域,每个区域包含4个可重构模块。本设计方法可以降低嵌入式系统开发复杂度、提高系统灵活性、降低开发成本、缩短开发周期以及减少系统功耗。
基于EAPR(early access partial reconfiguration)動態部分重構(dynamic partial reconfiguration,DPR)方法,研究瞭在 FPGA上實現自重構嵌入式繫統的設計方法。該方法運用 Xilinx的 ISE12.4開髮工具,調用已有 IP 覈,搭建包含用戶定製IP覈的自重構嵌入式繫統硬件平檯,併在Virtex5 FPGA上驗證。設計中運用瞭二維重構技術,劃分瞭3箇可重構區域,每箇區域包含4箇可重構模塊。本設計方法可以降低嵌入式繫統開髮複雜度、提高繫統靈活性、降低開髮成本、縮短開髮週期以及減少繫統功耗。
기우EAPR(early access partial reconfiguration)동태부분중구(dynamic partial reconfiguration,DPR)방법,연구료재 FPGA상실현자중구감입식계통적설계방법。해방법운용 Xilinx적 ISE12.4개발공구,조용이유 IP 핵,탑건포함용호정제IP핵적자중구감입식계통경건평태,병재Virtex5 FPGA상험증。설계중운용료이유중구기술,화분료3개가중구구역,매개구역포함4개가중구모괴。본설계방법가이강저감입식계통개발복잡도、제고계통령활성、강저개발성본、축단개발주기이급감소계통공모。
On the basis of Dynamic Partial Reconfiguration (DPR ) method Early Access Partial Reconfiguration (EAPR),design method of self-reconfiguration embedded system implemented on FPGA is studied.The hardware platform of the embedded system containing a custom-made IP is built by integrating merchant IPs resorting to the development tool ISE12.4 provided by Xilinx.Two-dimension reconfiguration technology is used in the design of the system which includes three Reconfigurable Partitions (RPs)and four Reconfigurable Modules (RMs)are available to each RP.Afterward,it is implemented on Virtex5 FPGA to verify the feasibility of the method.Via this method,the development complexity is reduced while development flexibility is improved,achieving lower cost,less time to market and power consumption reduction.
