CAJ | 학술논문

随着MOS制造工艺的不断发展，晶体管的特征尺寸越来越小，SRAM存储单元对制造工艺的要求也越来越高，功耗问题也越来越突出，该文设计的新型8管采用单个位线来进行读写操作，在两个交叉耦合的反相器之间加入PMOS晶体管来提高写能力。仿真的结果表明：与传统6管和7管相比，这种8管呈现出更好的读噪声容限、写裕度和保持存储数据的能力。
수착MOS제조공예적불단발전，정체관적특정척촌월래월소，SRAM존저단원대제조공예적요구야월래월고，공모문제야월래월돌출，해문설계적신형8관채용단개위선래진행독사조작，재량개교차우합적반상기지간가입PMOS정체관래제고사능력。방진적결과표명：여전통6관화7관상비，저충8관정현출경호적독조성용한、사유도화보지존저수거적능력。
As the CMOS process technology is continuingly developing, SRAM cell is more and more susceptive to increased pro?cess variation. The power consumption is becoming an important source. The proposed 8T SRAM cell uses a single-bit line struc?ture to perform read and write operation. The design improves the write ability by breaking-up the feedback loop of the inverter pair. The simulations show the proposed 8T cell offer better read static noise margin and write margin. Besides, the proposed cell has a significant improvement in HSNM.