现代电子技术
現代電子技術
현대전자기술
MODERN ELECTRONICS TECHNIQUE
2015年
16期
106-109
,共4页
数/模转换器%分段式电流舵%改进型Fibonacci数列%SoC
數/模轉換器%分段式電流舵%改進型Fibonacci數列%SoC
수/모전환기%분단식전류타%개진형Fibonacci수렬%SoC
digital-to-analog converter%segmented current steering%improved Fibonacci series%system on chip
针对SoC中DAC设计越来越受面积和功耗的制约,采用分段式结构,提出一种应用于SoC模拟输出前端的12位100 MS/s电流舵型D/A转换器,其中高6位为温度计码,低6位为改进型Fibonacci数列,其减小了DAC的面积和毛刺.电路基于SMIC 0.13 μm CMOS工艺,在1.2 V/3.3 V(数字/模拟)双电源供电下,满摆幅输出电流20 mA.在100 MHz采样频率、49.7 MHz输入信号下,无杂散动态范围(SFDR)达到89.448 dB,INL和DNL均小于0.5 LSB.
針對SoC中DAC設計越來越受麵積和功耗的製約,採用分段式結構,提齣一種應用于SoC模擬輸齣前耑的12位100 MS/s電流舵型D/A轉換器,其中高6位為溫度計碼,低6位為改進型Fibonacci數列,其減小瞭DAC的麵積和毛刺.電路基于SMIC 0.13 μm CMOS工藝,在1.2 V/3.3 V(數字/模擬)雙電源供電下,滿襬幅輸齣電流20 mA.在100 MHz採樣頻率、49.7 MHz輸入信號下,無雜散動態範圍(SFDR)達到89.448 dB,INL和DNL均小于0.5 LSB.
침대SoC중DAC설계월래월수면적화공모적제약,채용분단식결구,제출일충응용우SoC모의수출전단적12위100 MS/s전류타형D/A전환기,기중고6위위온도계마,저6위위개진형Fibonacci수렬,기감소료DAC적면적화모자.전로기우SMIC 0.13 μm CMOS공예,재1.2 V/3.3 V(수자/모의)쌍전원공전하,만파폭수출전류20 mA.재100 MHz채양빈솔、49.7 MHz수입신호하,무잡산동태범위(SFDR)체도89.448 dB,INL화DNL균소우0.5 LSB.
Since the design of DAC in SoC is more and more conditioned by area and power consumption,a 12-bit 100 MS/s current steering DAC applied to analog output front-end of SoC is proposed,in which a segmented architecture is employed. In this circuit,high 6-bit is thermometer code while low 6-bit is the improved Fibonacci Series which can cut down the area and glitch of DAC. Based upon SMIC 0.13μm CMOS process,the full-swing output current is 20 mA under the condition of 1.2 V/3.3 V dual power supply(digital and analog). Simulation results show that both INL and DNL are all lower than 0.5 LSB,and the SFDR is up to 89.448 dB under the condition of 49.7 MHz input signal frequency at 100MHz sampling rate.
