CAJ | 학술논문

为了使USB接口能适应多样化的外围设备，以USB高速设备接口芯片的SoC模型为基础，设计并实现了一种从属结构的数据传输模式，详细分析了从模式传输原理、端点工作机制、固件程序设计、仿真平台设计及仿真结果。以Verilog硬件描述语言设计了仿真平台，包括例化DesignWare库中的USB主机验证IP核作为数据发送接收的主机端，外部数据存储器作为外设数据的中转站，并通过比较主机端的发送和回读数据验证了设计的正确性。结果表明，外部控制器可控制处于从模式的USB设备接口芯片，实现数据在主机与设备之间的交互，此模式下能够有效地提高数据的传输速率，改善数据传输系统的工作效率。
위료사USB접구능괄응다양화적외위설비，이USB고속설비접구심편적SoC모형위기출，설계병실현료일충종속결구적수거전수모식，상세분석료종모식전수원리、단점공작궤제、고건정서설계、방진평태설계급방진결과。이Verilog경건묘술어언설계료방진평태，포괄례화DesignWare고중적USB주궤험증IP핵작위수거발송접수적주궤단，외부수거존저기작위외설수거적중전참，병통과비교주궤단적발송화회독수거험증료설계적정학성。결과표명，외부공제기가공제처우종모식적USB설비접구심편，실현수거재주궤여설비지간적교호，차모식하능구유효지제고수거적전수속솔，개선수거전수계통적공작효솔。
In order to make the USB interface meet the requirements of diverse peripheral equipments, a slave structure of data transmission mode based on the SoC model of high speed USB device interface chip is designed and implemented. The slave mode transmission principle, the endpoint working mechanism, the firmware design, the simulation platform design, and the simulation results are described in detail. The simulation platform is built by Verilog hardware description language, including using the host verification IP core from DesignWare library as the host end for data transmitting and receiving, and using the external data RAM as the transfer station for peripheral data. The correctness of design is verified by comparing the original data transmitted from the host end and the data read back. The results show that the slave mode of the USB device interface chip can be controlled by the external controller to realize data interaction between the host and the device, helping to increase the data transmission rate and improve the efficiency of data transmission systems.