周口师范学院学报
週口師範學院學報
주구사범학원학보
Journal of Zhoukou Normal University
2011年
5期
32~35
,共null页
循环冗余校验 生成多项式 Verilog HDL语言 现场可编程门阵列
循環冗餘校驗 生成多項式 Verilog HDL語言 現場可編程門陣列
순배용여교험 생성다항식 Verilog HDL어언 현장가편정문진렬
cyclic redundancy check; generator polynomial; Verilog HDL; Field Programmable Gate Array
介绍了循环冗余校验原理，并以CRC-16生成多项式为例，用Verilog HDL硬件描述语言描述该算法．采用Quartus Ⅱ8．0进行综合、仿真，并用CycloneⅡ系列的EP2C35F672C6器件适配和编程下载，在DE2开发板上实现．该CRC模块既是CRC校验生成模块，又是CRC校验检错模块．另外，该CRC模块还可以封装成具有Avalon总线接口的自定义组件IP核，从而可以重复利用．实验结果表明，该校验器速度快，占用资源少，并在实际中得到了应用．
介紹瞭循環冗餘校驗原理，併以CRC-16生成多項式為例，用Verilog HDL硬件描述語言描述該算法．採用Quartus Ⅱ8．0進行綜閤、倣真，併用CycloneⅡ繫列的EP2C35F672C6器件適配和編程下載，在DE2開髮闆上實現．該CRC模塊既是CRC校驗生成模塊，又是CRC校驗檢錯模塊．另外，該CRC模塊還可以封裝成具有Avalon總線接口的自定義組件IP覈，從而可以重複利用．實驗結果錶明，該校驗器速度快，佔用資源少，併在實際中得到瞭應用．
개소료순배용여교험원리，병이CRC-16생성다항식위례，용Verilog HDL경건묘술어언묘술해산법．채용Quartus Ⅱ8．0진행종합、방진，병용CycloneⅡ계렬적EP2C35F672C6기건괄배화편정하재，재DE2개발판상실현．해CRC모괴기시CRC교험생성모괴，우시CRC교험검착모괴．령외，해CRC모괴환가이봉장성구유Avalon총선접구적자정의조건IP핵，종이가이중복이용．실험결과표명，해교험기속도쾌，점용자원소，병재실제중득도료응용．
Cyclic Redundancy Check （CRC） is a type of channel coding technology used for error detection and control in digital communication. After introducing the principle of CRC, taking CRC - 16 polynomial as an example, the author described the CRC algorithm using hardware description language Verilog HDL. CRC module is synthesized, fitted and simulated by Quartus Ⅱ 8.0, programmed into the Cyclone II family device EP2C35F672C6 and implemented on DE2 board. The module is the combination of CRC generator and CRC checker. In addition to, this CRC module can be packed as a custom component with Avalon - MM interface and be shared with other designer. The result of the experiment showed that this CRC module has a high speed, less resources consumption, and it is used in actual application.
