CAJ | 학술논문

提出一种电容片内集成、高效率升压模式的DC－DC电源管理芯片，较普通结构相比，文中提出的电路结构具有6组2×，3组3×，2组4×升压模型共11种工作模式，并具有低纹波等优点。通过MIM电容与积累型NMOS电容串联的方式，提高单位面积容值，使得总电容面积大幅减小。采用SMIC 0.18μm CMOS工艺，利用Cadence工具对电路进行仿真验证，所提出自适应开关电容升压电路，在输出电压为3 V时，其效率最高可达到83.6％。在开关频率为20 MHz时，输入电压范围为1～1.8 V，所需总片内集成电容总面积为900μm ×900μm，输出电压纹波＜40 mV。
제출일충전용편내집성、고효솔승압모식적DC－DC전원관리심편，교보통결구상비，문중제출적전로결구구유6조2×，3조3×，2조4×승압모형공11충공작모식，병구유저문파등우점。통과MIM전용여적루형NMOS전용천련적방식，제고단위면적용치，사득총전용면적대폭감소。채용SMIC 0.18μm CMOS공예，이용Cadence공구대전로진행방진험증，소제출자괄응개관전용승압전로，재수출전압위3 V시，기효솔최고가체도83.6％。재개관빈솔위20 MHz시，수입전압범위위1～1.8 V，소수총편내집성전용총면적위900μm ×900μm，수출전압문파＜40 mV。
A high-efficiency boost mode electronic power management chip with on-chip capacitor is proposed. Compared to the conventional structure, the presented circuit has 11 patterns: six groups of 2 ×, 3 groups of 3 ×, and 2 groups of 4 × booster modes.It also has the advantage of low-ripple and so on.The chip size is greatly re-duced by using MIM capacitance and accumulation NMOS capacitance in series, which increases the capacity value per unit area.The proposed circuit is implemented using SMIC 0.18 μm CMOS process.The Cadence simulation results show that the efficiency is up to 83.6% when the output voltage is 3 V.When the switching frequency is 20 MHz with the input voltage from 1 V to 1.8 V, the area of overall capacitor integrated on chip is 900 μm × 900 μm and the output ripple is less than 40 mV.