舰船电子工程
艦船電子工程
함선전자공정
Ship Electronic Engineering
2015年
9期
75-77
,共3页
赵亚范%王坤%杨帆%毕涛
趙亞範%王坤%楊帆%畢濤
조아범%왕곤%양범%필도
FPGA%校验编码%并行传输%RS232
FPGA%校驗編碼%併行傳輸%RS232
FPGA%교험편마%병행전수%RS232
FPGA%check code%parellel data transmission%RS232
该系统以 FPGA 为核心，通过两个彼此独立的 FPGA 核心板构成高速并行数据传输系统的发送端和接收端。传输协议采用12bit 有效数据带宽、5位循环冗余码进行校验编码（CRC），总线传输速率可达24Mbps 以上。接收端成功接收完数据后可通过液晶屏显示数据内容，通过 RS232总线上传至 PC 机进行分析，传输速率9600bps 。传输过程中通过核心板上的 LED 指示灯指示传输线路状态。整个系统模块化程度好、集成度高，充分发挥单片机灵活实用的特点和运算速度快的优势。
該繫統以 FPGA 為覈心，通過兩箇彼此獨立的 FPGA 覈心闆構成高速併行數據傳輸繫統的髮送耑和接收耑。傳輸協議採用12bit 有效數據帶寬、5位循環冗餘碼進行校驗編碼（CRC），總線傳輸速率可達24Mbps 以上。接收耑成功接收完數據後可通過液晶屏顯示數據內容，通過 RS232總線上傳至 PC 機進行分析，傳輸速率9600bps 。傳輸過程中通過覈心闆上的 LED 指示燈指示傳輸線路狀態。整箇繫統模塊化程度好、集成度高，充分髮揮單片機靈活實用的特點和運算速度快的優勢。
해계통이 FPGA 위핵심，통과량개피차독립적 FPGA 핵심판구성고속병행수거전수계통적발송단화접수단。전수협의채용12bit 유효수거대관、5위순배용여마진행교험편마（CRC），총선전수속솔가체24Mbps 이상。접수단성공접수완수거후가통과액정병현시수거내용，통과 RS232총선상전지 PC 궤진행분석，전수속솔9600bps 。전수과정중통과핵심판상적 LED 지시등지시전수선로상태。정개계통모괴화정도호、집성도고，충분발휘단편궤령활실용적특점화운산속도쾌적우세。
This system takes FPGA as the core ,while the sender and the receiver of high‐speed parallel data transmis‐sion system have been constituted by two independent FPGA core boards .Transfer protocol adopts 12 bit effective data bandwidth and five cyclic redundancy check code(CRC) ,and transmission rate of bus can reach more than 24 megabits per second .The receiver can be displayed panel data content by LCD after successfully receiving the data which is analyzed by uploading to the PC through the RS232 bus with the transmission rate 9600 BPS .The state of transmission lines is indicated through the LED indicator light on the core board in the process of transmission .The whole system with good modular de‐gree and high integration plays full advantage of flexible and fast practical computing speed .
