CAJ | 학술논문

为了研究可控硅结构的静电释放保护器件结构尺寸与性能的关系，采用0.5μm的5 V/18 V CDMOS工艺流片两组SCR ESD器件，使用传输线脉冲测试系统测试器件的性能参数。实验结果表明，随着N阱内P+区和P阱内N+区间距从6μm增加到22μm，ESD器件的维持电压线性增大，从2.29 V升高到9.64 V，幅度达421%；单位面积的失效电流线性减小，幅度约为63%。分析与仿真结果表明，该线性关系具有普遍适用性，可用于调节器件的健壮性和功率耗散能力，满足智能功率集成电路的高压ESD防护需求。另一组随着P阱内P+区和N+区间距增大，维持电压和失效电流呈现非线性的变化，但触发电压迅速降低，可用于实现高压SCR ESD器件的低触发电压设计。
위료연구가공규결구적정전석방보호기건결구척촌여성능적관계，채용0.5μm적5 V/18 V CDMOS공예류편량조SCR ESD기건，사용전수선맥충측시계통측시기건적성능삼수。실험결과표명，수착N정내P+구화P정내N+구간거종6μm증가도22μm，ESD기건적유지전압선성증대，종2.29 V승고도9.64 V，폭도체421%；단위면적적실효전류선성감소，폭도약위63%。분석여방진결과표명，해선성관계구유보편괄용성，가용우조절기건적건장성화공솔모산능력，만족지능공솔집성전로적고압ESD방호수구。령일조수착P정내P+구화N+구간거증대，유지전압화실효전류정현비선성적변화，단촉발전압신속강저，가용우실현고압SCR ESD기건적저촉발전압설계。
Electrostatic discharge (ESD) properties of high voltage silicon controlled rectifier (HV-SCR) ESD devices can be adjusted by their key layout parameters. Two groups of HV-SCR ESD devices with particular layout parameters were fabricated in 0.5μm 5 V/18 V CDMOS process, and their current-voltage curves, holding voltages, and failure currents were investigated and characterized by a transmission line pulse test system, respectively. Experimental data shows that with increasing layout spacing from P+ implant in N well to N+ implant in P well, the holding voltage grows linearly from 2.29 V to 9.64 V, as much as 421%, but the failure current per area decreases linearly about 63%. Using analysis and simulation results, two equations for the holding voltage and failure current were generalized properly. They can be used as a guideline to adjust ESD robustness and performance of HV- SCR ESD devices in smart power integrated circuits. However, with increasing layout spacing from P+ implant to N+ implant in P well, this phenomenon can’t be found, but the trigger voltages of the devices decrease sharply, which can be used for low trigger voltage design of HV-SCR ESD devices.