CAJ | 학술논문

对暗原色先验算法中引导滤波器进行改进，提出了一种快速计算像素模板均值的方法，并设计了这种改进方法的电路结构。模板均值是通过存储局部窗口第一列和最后一列的和，加上/减去其相应列中某个像素点的值得到，这种计算方法不仅能够在不改变滤波效果的前提下使计算复杂度降低到常数级，而且更符合FPGA的并行流水设计。实验结果表明，在Altera公司CycloneII系列的EP2C70的FPGA开发板上的逻辑和内存的使用量分别占7.9%和35%，低端FPGA能够满足需求，每秒可处理100帧1024′1024的图像，实时性完全达到要求。
대암원색선험산법중인도려파기진행개진，제출료일충쾌속계산상소모판균치적방법，병설계료저충개진방법적전로결구。모판균치시통과존저국부창구제일렬화최후일렬적화，가상/감거기상응렬중모개상소점적치득도，저충계산방법불부능구재불개변려파효과적전제하사계산복잡도강저도상수급，이차경부합FPGA적병행류수설계。실험결과표명，재Altera공사CycloneII계렬적EP2C70적FPGA개발판상적라집화내존적사용량분별점7.9%화35%，저단FPGA능구만족수구，매초가처리100정1024′1024적도상，실시성완전체도요구。
Based on dark channel prior algorithm to improve guide filter, a fast method of calculating the mean pixel tem-plate is proposed, and the circuit structure of the improved method is designed. The mean template is achieved by means of storing the sum of the first and the last column of local window, and then plus/minus the corresponding column in the value of a pixel. Under the premise of unchanging the filter effect, this calculation method can effectively reduce the com-putational complexity to constant level and more fit the parallel flow design of FPGA. Experimental results show that the series EP2C70 FPGA development board of Altera Corporation CycloneII, its usage of logic and memory is 7.9% and 35% respectively, the low-end FPGA can satisfy the demands, 100 frames 1 024 ′ 1 024 images can be handled in every second, and real-time fully meet the requirements.