电子技术
電子技術
전자기술
Electronic Technology
2015年
9期
6-8
,共3页
FPGA%直接数字频率合成(DDS)%线性调频脉冲信号
FPGA%直接數字頻率閤成(DDS)%線性調頻脈遲信號
FPGA%직접수자빈솔합성(DDS)%선성조빈맥충신호
FPGA%Direct Digital Frequency Synthesize (DDS)%Chirp Signal
在科研工作中经常需要频率、相位和幅值能够数字调制的线性调频脉冲信号源。文章设计实现了基于直接数字频率合成（DDS）技术的线性调频脉冲信号的产生，介绍了该信号发生器的工作原理、系统组成、接口设计以及软件算法流程，提出了利用计数器控制波形读写和系统时序的方式来实现输出信号的数字调制。实测结果验证了设计方案的合理性和正确性，精确实现了对系统输出波形参数的动态可调。
在科研工作中經常需要頻率、相位和幅值能夠數字調製的線性調頻脈遲信號源。文章設計實現瞭基于直接數字頻率閤成（DDS）技術的線性調頻脈遲信號的產生，介紹瞭該信號髮生器的工作原理、繫統組成、接口設計以及軟件算法流程，提齣瞭利用計數器控製波形讀寫和繫統時序的方式來實現輸齣信號的數字調製。實測結果驗證瞭設計方案的閤理性和正確性，精確實現瞭對繫統輸齣波形參數的動態可調。
재과연공작중경상수요빈솔、상위화폭치능구수자조제적선성조빈맥충신호원。문장설계실현료기우직접수자빈솔합성（DDS）기술적선성조빈맥충신호적산생，개소료해신호발생기적공작원리、계통조성、접구설계이급연건산법류정，제출료이용계수기공제파형독사화계통시서적방식래실현수출신호적수자조제。실측결과험증료설계방안적합이성화정학성，정학실현료대계통수출파형삼수적동태가조。
The chirp signal source with its frequency, phase and amplitude could be digital modulated is always needed in scientific research. The paper designs and implements the generation of chirp signal on the basis of Direct Digital Frequency Synthesis (DDS), and introduces the work principle, system composition, interface design and software algorithm flow of the chirp signal generator, and puts forward the way of the read-write control of waveform and the system sequential to achieve output signal could be digital modulated by using counter. The reasonability and correctness of the design plan are verified by the measured results, and the output waveform parameters of the system which are programmable and adjustable can be realized accurately.
