信息通信
信息通信
신식통신
Information & Communications
2015年
9期
80-81
,共2页
GMR-13G标准%LDPC%编码器%FPGA
GMR-13G標準%LDPC%編碼器%FPGA
GMR-13G표준%LDPC%편마기%FPGA
GMR-1 3G standard%LDPC%encoder%FPGA
针对GMR-1 3G标准中的LDPC码,设计实现了一种多码长、多码率的编码器,采用并行处理的方式,降低了编码的时延,提高了编码的速率.使用Quartus II工具进行功能仿真,验证了编码的正确性和有效性.
針對GMR-1 3G標準中的LDPC碼,設計實現瞭一種多碼長、多碼率的編碼器,採用併行處理的方式,降低瞭編碼的時延,提高瞭編碼的速率.使用Quartus II工具進行功能倣真,驗證瞭編碼的正確性和有效性.
침대GMR-1 3G표준중적LDPC마,설계실현료일충다마장、다마솔적편마기,채용병행처리적방식,강저료편마적시연,제고료편마적속솔.사용Quartus II공구진행공능방진,험증료편마적정학성화유효성.
According to the LDPC encoder of GMR-1 3G standard, a new design scheme for the common LDPC encoder of mul-ti-rate, multi-length based on FPGA is proposed. This encoder has realized universal LDPC code encoder, reduced the delay of encoding and improved the efficiency of encoder by using parallel structure. The software of Quartus II is used to do the syn-thesis simulation.Through simulation and experiment, the correctness and validity of this encoder are testified.
