现代电子技术
現代電子技術
현대전자기술
Modern Electronics Technique
2015年
19期
135-139
,共5页
DDR%高速信号%封装布线%信号串扰影响%电路设计
DDR%高速信號%封裝佈線%信號串擾影響%電路設計
DDR%고속신호%봉장포선%신호천우영향%전로설계
DDR%high-speed signal%packaging wiring%signal crosstalk influence%circuit design
不同于印制电路板的制作工艺,芯片封装基板的走线更细,线间距更窄。狭小的布线空间使传输线效应更为明显,而且封装设计的好坏直接影响芯片是否可以正常工作,同时芯片成本的控制要求布线层尽量要最少。这些问题使得高速信号布线面临严峻的挑战。在国家科技重大专项的资助下,使用全波电磁场仿真工具进行建模分析,研究了布线中线宽、线间距和参考地对信号传输质量和信号间串扰的影响,并且基于一款低功耗DDR高速芯片的双层封装布线设计,在实际设计方案中对分析结果进行了仿真验证,最终得到了一种高质量、低成本封装基板高速布线方案,速率达到1333 Mb/s。
不同于印製電路闆的製作工藝,芯片封裝基闆的走線更細,線間距更窄。狹小的佈線空間使傳輸線效應更為明顯,而且封裝設計的好壞直接影響芯片是否可以正常工作,同時芯片成本的控製要求佈線層儘量要最少。這些問題使得高速信號佈線麵臨嚴峻的挑戰。在國傢科技重大專項的資助下,使用全波電磁場倣真工具進行建模分析,研究瞭佈線中線寬、線間距和參攷地對信號傳輸質量和信號間串擾的影響,併且基于一款低功耗DDR高速芯片的雙層封裝佈線設計,在實際設計方案中對分析結果進行瞭倣真驗證,最終得到瞭一種高質量、低成本封裝基闆高速佈線方案,速率達到1333 Mb/s。
불동우인제전로판적제작공예,심편봉장기판적주선경세,선간거경착。협소적포선공간사전수선효응경위명현,이차봉장설계적호배직접영향심편시부가이정상공작,동시심편성본적공제요구포선층진량요최소。저사문제사득고속신호포선면림엄준적도전。재국가과기중대전항적자조하,사용전파전자장방진공구진행건모분석,연구료포선중선관、선간거화삼고지대신호전수질량화신호간천우적영향,병차기우일관저공모DDR고속심편적쌍층봉장포선설계,재실제설계방안중대분석결과진행료방진험증,최종득도료일충고질량、저성본봉장기판고속포선방안,속솔체도1333 Mb/s。
Compared with manufacture technique of printed circuit board,thinner wirings and more narrow wire spacing on the chip package substrate are needed. The narrow wiring space makes the transmission line effect more obvious. The packaging design impacts chip performance directly. The least wiring layers are needed for cost control of chip,which make the wiring of high?speed signal be faced with crucial challenge. This work is supported by the“National Science and Technology Major Proj?ect”. Modeling analysis is conducted with the full?wave electromagnetic field simulation tools to research the influences of wires′central line width,wire spacing and reference ground on signal transmission quality and signal crosstalk. Based on the double?layer packaging wiring design of a high?speed LPDDR chip,the analysis results were verified by simulation in actual design scheme. A high?speed wiring scheme of packaging substrate with high quality and low cost was obtained,whose rate reaches 1 333 Mb/s.