现代电子技术
現代電子技術
현대전자기술
Modern Electronics Technique
2015年
19期
33-36,39
,共5页
FFT%测频%流水结构%并行处理模式%FPGA
FFT%測頻%流水結構%併行處理模式%FPGA
FFT%측빈%류수결구%병행처리모식%FPGA
FFT%frequency measurement%pipeline structure%parallel processing mode%FPGA
以雷达侦察接收机为应用背景,利用FPGA芯片并行工作的特性,设计一种并行加流水线处理模式的FFT处理器结构,实现宽带数字测频。在2.4 GSPS采样率下,选取基?2频域抽取(DIF)算法,采用每通道512点流水结构FFT、8通道并行处理的设计思路,以达到单通道4096点FFT的处理效果。在保证分辨率的同时,采样数据能够被实时处理。仿真结果显示,在300 MHz时钟下,FPGA完成4096个数据的缓存和FFT运算只需要2.1μs,满足雷达侦察接收机对数据处理速度的要求。
以雷達偵察接收機為應用揹景,利用FPGA芯片併行工作的特性,設計一種併行加流水線處理模式的FFT處理器結構,實現寬帶數字測頻。在2.4 GSPS採樣率下,選取基?2頻域抽取(DIF)算法,採用每通道512點流水結構FFT、8通道併行處理的設計思路,以達到單通道4096點FFT的處理效果。在保證分辨率的同時,採樣數據能夠被實時處理。倣真結果顯示,在300 MHz時鐘下,FPGA完成4096箇數據的緩存和FFT運算隻需要2.1μs,滿足雷達偵察接收機對數據處理速度的要求。
이뢰체정찰접수궤위응용배경,이용FPGA심편병행공작적특성,설계일충병행가류수선처리모식적FFT처리기결구,실현관대수자측빈。재2.4 GSPS채양솔하,선취기?2빈역추취(DIF)산법,채용매통도512점류수결구FFT、8통도병행처리적설계사로,이체도단통도4096점FFT적처리효과。재보증분변솔적동시,채양수거능구피실시처리。방진결과현시,재300 MHz시종하,FPGA완성4096개수거적완존화FFT운산지수요2.1μs,만족뢰체정찰접수궤대수거처리속도적요구。
Based on the application background of radar reconnaissance receiver and the parallel operation behavior of FPGA chip,an FFT processor structure combining the parallel processing mode with pipeline processing mode was designed to realize the digital frequency measurement of broadband. At the sampling rate of 2.4 GSPS,the radix?2?based decimation in frequency (DIF)algorithm is selected,the design thought of 512?point pipeline structure FFT for each channel and 8?channel parallel pro?cessing is adopted to achieve the processing effect of 4 096?point FFT in single channel. The sampling data can be processed in real time while the resolution is ensured. The simulation results show that it only takes 2.1 μs for FPGA to finish the 4 096 data caching and FFT operation at 300 MHz,which can meet the requirements of radar reconnaissance receiver to data processing speed.