湖南大学学报（自然科学版）
湖南大學學報（自然科學版）
호남대학학보（자연과학판）
Journal of Hunan University (Natural Sciences)
2015年
10期
78-82
,共5页
噪声减少%转换电路%电平转换%同步开关噪声(SSN)%延时功耗积%地弹效应%功耗%阈值电压
譟聲減少%轉換電路%電平轉換%同步開關譟聲(SSN)%延時功耗積%地彈效應%功耗%閾值電壓
조성감소%전환전로%전평전환%동보개관조성(SSN)%연시공모적%지탄효응%공모%역치전압
noise abatement%switching circuits%level transform%Simultaneous Switch Noise(SSN)%delay-power product%ground bounce%power consumption%threshold voltage
传统多电源系统数字输出端口存在上拉、下拉竞争和上升沿与下降沿的严重不对称等问题,使得延时功耗积很大；而电压波动和误触发导致系统 SSN 噪声较大。针对这2个问题,提出一种采用快速低转高电平转换电路结构和抗地弹效应输出电路的新型输出端口电路结构,在 smic18mmrf工艺下流片。测试结果表明,电平转换单元功耗延时积较传统结构减小5%~15%,SSN噪声幅度减少30%以上,有效提高了输出端口电路性能。
傳統多電源繫統數字輸齣耑口存在上拉、下拉競爭和上升沿與下降沿的嚴重不對稱等問題,使得延時功耗積很大；而電壓波動和誤觸髮導緻繫統 SSN 譟聲較大。針對這2箇問題,提齣一種採用快速低轉高電平轉換電路結構和抗地彈效應輸齣電路的新型輸齣耑口電路結構,在 smic18mmrf工藝下流片。測試結果錶明,電平轉換單元功耗延時積較傳統結構減小5%~15%,SSN譟聲幅度減少30%以上,有效提高瞭輸齣耑口電路性能。
전통다전원계통수자수출단구존재상랍、하랍경쟁화상승연여하강연적엄중불대칭등문제,사득연시공모적흔대；이전압파동화오촉발도치계통 SSN 조성교대。침대저2개문제,제출일충채용쾌속저전고전평전환전로결구화항지탄효응수출전로적신형수출단구전로결구,재 smic18mmrf공예하류편。측시결과표명,전평전환단원공모연시적교전통결구감소5%~15%,SSN조성폭도감소30%이상,유효제고료수출단구전로성능。
In the digital output port of the traditional multi-power system,there are pull-up-drop-down competition and serious asymmetry between positive edge and negative edge,which results in a large delay-power product,while the large voltage fluctuation and spurious triggering result in a high SSN noise.To deal with these problems,this paper proposed a novel output circuit architecture,which employs a quick voltage level transform circuit to reduce the delay-power product and a resistance of ground bounce output structure to reduce the SSN noise.The output circuit was fabricated by SMIC18mmrf process,and the test shows that the delay-power consumption product is reduced by 5%~1 5% and SNN noise amplitude is low-ered by 30%,compared with the traditional circuit,which indicates the high performance of the novel out-put circuit.
