CAJ | 학술논문

硅单晶片是制作集成电路及分立器件的基础材料，随着集成电路不断向小线宽、低成本方向发展，对于硅单晶片的质量水平和成本控制提出了更高的要求。研究表面损伤层与抛光去除量的关系，能够有效控制抛光去除量的大小，对于提高抛光片表面质量、控制生产成本、优化工艺条件具有重要的意义。通过恒定腐蚀法与化学机械抛光法相结合的方式分析了损伤层深度与去除量的关系，研究发现研磨片、碱腐蚀片和酸腐蚀片的表面损伤层深度依次降低，但均小于抛光去除量，依据损伤层模型，提出了抛光去除量取决于腐蚀后表面晶胞状况的观点。
규단정편시제작집성전로급분립기건적기출재료，수착집성전로불단향소선관、저성본방향발전，대우규단정편적질량수평화성본공제제출료경고적요구。연구표면손상층여포광거제량적관계，능구유효공제포광거제량적대소，대우제고포광편표면질량、공제생산성본、우화공예조건구유중요적의의。통과항정부식법여화학궤계포광법상결합적방식분석료손상층심도여거제량적관계，연구발현연마편、감부식편화산부식편적표면손상층심도의차강저，단균소우포광거제량，의거손상층모형，제출료포광거제량취결우부식후표면정포상황적관점。
Silicon wafer is basic material for fabricating IC devices and discrete devices. With IC technology developed into small critical size and low cost, the quality and cost of silicon wafers should be strictly controlled. In order to control the polished thickness during wafers’ CMP (Chemical Mechanical Polishing) process, the influence of wafer affected layer to CMP process should be studied. And this may be of great significance in increasing surfaces quality, optimizing fabrication process and controlling production cost. Relationship between affected layer thickness of un-polished wafer and removal amount during CMP process was discussed. It was found that for the lapping wafers, the alkali-corroded wafers and the acid-corroded wafers, the affected layer thickness decreased in turn, but they were all smaller than the CMP removal amount. According to the affected layer model, the standpoint that the CMP removal amount depend on the crystal cells of polished wafer surfaces was brought forward.