降维的对偶忆阻混沌电路及其 FPGA 的实现
강유적대우억조혼돈전로급기 FPGA 적실현
A Dual Memristive Chaotic Circuit of Dimensionality Reduction and its FPGA Realization
  • 万方数据
    杭州师范大学学报（自然科学版） 항주사범대학학보（자연과학판）
    Journal of Hangzhou Normal University (Natural Sciences Edition)
    2015年 6期 656-658,668 ,共4页

    詹信雄%许碧荣%黄聪%邱蓉%刘志国

    첨신웅%허벽영%황총%구용%류지국

    忆阻器%对偶%混沌电路%降维%FPGA 憶阻器%對偶%混沌電路%降維%FPGA
    억조기%대우%혼돈전로%강유%FPGA
    memristor%dual%chaotic circuit%dimensionality reduction%FPGA
    提出了一个对偶忆阻器混沌电路，对其降维研究的结果表明降维的对偶忆阻混沌电路与对偶蔡氏混沌电路一致。并利用FPGA实现了降维的忆阻混沌电路，说明此忆阻混沌电路可数字化实现。
    제출료일개대우억조기혼돈전로，대기강유연구적결과표명강유적대우억조혼돈전로여대우채씨혼돈전로일치。병이용FPGA실현료강유적억조혼돈전로，설명차억조혼돈전로가수자화실현。
    In this paper ,a dual memristive chaotic circuit is presented .Its dimensionality reduction is studied ,and it is obtained that the dual memristive chaotic circuit of dimensionality reduction is consistent with the Chua's dual chaotic circuit . Then ,FPGA is used to implement this chaotic circuit ,and it expresses that the memristive chaotic circuits can be realized by digital way .
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