CAJ | 학술논문

FPGA的应用使得电路设计及实现具有更大的灵活性，但同时由于其结构特性，FPGA也更易受到外界的影响，发生瞬态故障，引起软错误。FPGA动态可重构功能的出现及应用为提高FPGA电路设计可靠性提供了一种解决方案。文章提出了一种针对嵌入式软核的重构容错方案，以三模冗余为基础，通过处理器之间的相互控制方法，在实现快速检错的同时，降低了硬件开销及时间开销。
FPGA적응용사득전로설계급실현구유경대적령활성，단동시유우기결구특성，FPGA야경역수도외계적영향，발생순태고장，인기연착오。FPGA동태가중구공능적출현급응용위제고FPGA전로설계가고성제공료일충해결방안。문장제출료일충침대감입식연핵적중구용착방안，이삼모용여위기출，통과처리기지간적상호공제방법，재실현쾌속검착적동시，강저료경건개소급시간개소。
The application of field‐programmable gate array(FPGA) makes the design and implementa‐tion of circuit has greater flexibility .But because of its structural characteristics ,FPGA is affected easier by outside ,resulting in transient faults and soft errors . The application of FPGA dynamic reconfigurable function provides a solution for improving the reliability of FPGA circuit design .In this paper ,a reconfigurable fault‐tolerant triple modular redundancy (TMR) based scheme for embedded soft‐core processor is presented .The mutual control method between processors is designed and used . The presented scheme can ensure the rapid error detection and reduce hardware and time overhead .