CAJ | 학술논문

基于CSMC 0.5 um CMOS工艺设计了一种PSM(Pulse Skip Mode)调制电荷泵DC-DC升压芯片.优化整体结构使能控制最大程度上降低静态功耗,设计能够防止振荡器误操作的时钟逻辑控制电路、宽工作范围低温度系数的带隙基准和衬底最高电位选择电路,分别起到有效抑制纹波紊乱,减小开关切换时流过开关管的脉冲电流、拓宽芯片的工作温度范围和防止闩锁效应,减小芯片面积的作用.仿真结果表明所设计的改进措施使该芯片较传统的2倍升压电荷泵具有更低的稳定纹波、静态功耗和更宽的工作温度范围,进一步提高了升压电荷泵芯片的性能.
기우CSMC 0.5 um CMOS공예설계료일충PSM(Pulse Skip Mode)조제전하빙DC-DC승압심편.우화정체결구사능공제최대정도상강저정태공모,설계능구방지진탕기오조작적시종라집공제전로、관공작범위저온도계수적대극기준화츤저최고전위선택전로,분별기도유효억제문파문란,감소개관절환시류과개관관적맥충전류、탁관심편적공작온도범위화방지산쇄효응,감소심편면적적작용.방진결과표명소설계적개진조시사해심편교전통적2배승압전하빙구유경저적은정문파、정태공모화경관적공작온도범위,진일보제고료승압전하빙심편적성능.
A design of PSM (Pulse Skip Mode) boost DC-DC IC base on CSMC 0.5μm CMOS technology was presented. The circuit's overall structure was optimized to greatly reduce the static power. In the study, a clock logic control circuit which can prevent oscillator from accidental gesturing, a wide range low temperature coefficient band gap reference and a substrate maximum potential selector circuit were separately designed to effectively restrain ripple derangement, decrease the pulse current flow through the switching transistor, broaden the IC's temperature range, avoid latch up phenomenon and de-crease the chip area. As simulation results indicated, the proposed improvement measures enabled this IC's lower steady ripple, lower static power and wider working temperature range compared with traditional voltage doubling charge pumps, thus further improving the performance of boost charge pump chips.