计算机工程与应用
計算機工程與應用
계산궤공정여응용
COMPUTER ENGINEERING AND APPLICATIONS
2014年
6期
35-39,60
,共6页
数码印花%图像数据转置%实时%喷印速度%现场可编程门阵列(FPGA)
數碼印花%圖像數據轉置%實時%噴印速度%現場可編程門陣列(FPGA)
수마인화%도상수거전치%실시%분인속도%현장가편정문진렬(FPGA)
digital printing%image data transposition%real-time%printing speed%Field-Programmable Gate Array(FPGA)
针对PC无法实时按位转置大量图像数据而限制了数码印花机输出带宽和喷印速度的问题，设计了基于PowerPC处理器和Virtex-5系列FPGA的高速数据处理系统，运用FPGA实现了高效转置运算。为FPGA例化三个独立的DDR2控制器，通过控制器间的协同工作提高系统输出带宽；设计按位转置单元，将图像数据分块转置，利用DDR2控制器的突发传输高效地读写数据。性能测试结果表明FPGA的输出带宽高达327 Mb/s，数码印花机的喷印速度达249 m2/h，相比PC处理系统，在同等条件下性能提升明显。
針對PC無法實時按位轉置大量圖像數據而限製瞭數碼印花機輸齣帶寬和噴印速度的問題，設計瞭基于PowerPC處理器和Virtex-5繫列FPGA的高速數據處理繫統，運用FPGA實現瞭高效轉置運算。為FPGA例化三箇獨立的DDR2控製器，通過控製器間的協同工作提高繫統輸齣帶寬；設計按位轉置單元，將圖像數據分塊轉置，利用DDR2控製器的突髮傳輸高效地讀寫數據。性能測試結果錶明FPGA的輸齣帶寬高達327 Mb/s，數碼印花機的噴印速度達249 m2/h，相比PC處理繫統，在同等條件下性能提升明顯。
침대PC무법실시안위전치대량도상수거이한제료수마인화궤수출대관화분인속도적문제，설계료기우PowerPC처리기화Virtex-5계렬FPGA적고속수거처리계통，운용FPGA실현료고효전치운산。위FPGA례화삼개독립적DDR2공제기，통과공제기간적협동공작제고계통수출대관；설계안위전치단원，장도상수거분괴전치，이용DDR2공제기적돌발전수고효지독사수거。성능측시결과표명FPGA적수출대관고체327 Mb/s，수마인화궤적분인속도체249 m2/h，상비PC처리계통，재동등조건하성능제승명현。
In general, the output bandwidth and printing speed of digital inkjet printer are limited as PC isn’t capable of transposing large quantities of image data bit-by-bit in real-time. A new high-speed data processing system based on PowerPC processor and Virtex-5 series FPGA is proposed, and a high-efficiency transposition method is achieved by using FPGA. Three independent DDR2 controllers are instantiated inside FPGA and system output bandwidth is improved by the collaborative work among these controllers;bit-by-bit transposition unit is designed, image data is divided into small blocks and these blocks are efficiently read or written through burst transmission of DDR2 controllers. Performance testing results demonstrate that output bandwidth of FPGA is up to 327 Mb/s and printing speed of digital inkjet printer reaches 249 m2/h, which is much faster than PC processing system under the same conditions.
