现代电子技术
現代電子技術
현대전자기술
MODERN ELECTRONICS TECHNIQUE
2014年
9期
145-147,153
,共4页
CMOS电路%鉴相器%半速率结构%混合信号
CMOS電路%鑒相器%半速率結構%混閤信號
CMOS전로%감상기%반속솔결구%혼합신호
CMOS circuit%phase detector%half-rate architecture%mixed signal
鉴相器是高速时钟数据恢复环路的关键电路，其性能的优劣直接影响了整个系统的工作。通过系统分析，提出了一种全数字半速率鉴相器设计方案，按照全定制设计流程采用SMIC 0.18μm CMOS混合信号工艺完成了电路的设计、仿真。结果表明该电路在2.5 Gb/s收发器电路中可以稳定可靠地工作。
鑒相器是高速時鐘數據恢複環路的關鍵電路，其性能的優劣直接影響瞭整箇繫統的工作。通過繫統分析，提齣瞭一種全數字半速率鑒相器設計方案，按照全定製設計流程採用SMIC 0.18μm CMOS混閤信號工藝完成瞭電路的設計、倣真。結果錶明該電路在2.5 Gb/s收髮器電路中可以穩定可靠地工作。
감상기시고속시종수거회복배로적관건전로，기성능적우렬직접영향료정개계통적공작。통과계통분석，제출료일충전수자반속솔감상기설계방안，안조전정제설계류정채용SMIC 0.18μm CMOS혼합신호공예완성료전로적설계、방진。결과표명해전로재2.5 Gb/s수발기전로중가이은정가고지공작。
The phase detector is a critical part of high-speed clock and data recovery circuit. Its performance has great influence on the whole system. According to a system analysis,a design scheme of all-digital half-rate phase detector is proposed in this paper. According to the full custom design flow,the circuit design and simulation were accomplished with the process of SMIC 0.18 μm CMOS mixed-signal. The simulation result shows that the circuit can work stably in the 2.5 Gb/s transceiver circuit.
