现代电子技术
現代電子技術
현대전자기술
MODERN ELECTRONICS TECHNIQUE
2014年
7期
151-153,156
,共4页
CDC%亚稳态%同步%仿真
CDC%亞穩態%同步%倣真
CDC%아은태%동보%방진
CDC%metastability%synchronization%simulation
随着FPGA设计中的时钟频率越来越高，时钟方案越来越复杂，跨时钟域问题变成了设计和验证中的关键点。为了解决跨时钟域问题对FPGA设计造成功能错误，对跨时钟域信号采用两级寄存器或多级寄存器同步、握手协议和异步FIFO等同步方法；同时还提出了不检查时序、修改SDF文件和添加约束文件三种仿真中的技术，解决了跨时钟域产生的亚稳态现象对FPGA仿真验证造成的影响。
隨著FPGA設計中的時鐘頻率越來越高，時鐘方案越來越複雜，跨時鐘域問題變成瞭設計和驗證中的關鍵點。為瞭解決跨時鐘域問題對FPGA設計造成功能錯誤，對跨時鐘域信號採用兩級寄存器或多級寄存器同步、握手協議和異步FIFO等同步方法；同時還提齣瞭不檢查時序、脩改SDF文件和添加約束文件三種倣真中的技術，解決瞭跨時鐘域產生的亞穩態現象對FPGA倣真驗證造成的影響。
수착FPGA설계중적시종빈솔월래월고，시종방안월래월복잡，과시종역문제변성료설계화험증중적관건점。위료해결과시종역문제대FPGA설계조성공능착오，대과시종역신호채용량급기존기혹다급기존기동보、악수협의화이보FIFO등동보방법；동시환제출료불검사시서、수개SDF문건화첨가약속문건삼충방진중적기술，해결료과시종역산생적아은태현상대FPGA방진험증조성적영향。
With the increasing clock frequency in the FPGA design,the clock scheme is more and more complex,and the issue of crossing the clock domain becomes a key point in design and verification. In order to correct the function error in FPGA design generated by crossing clock domain,two-stage register or multi-stage register synchronization,hand-shake protocol and asynchronous FIFO are used for the signal crossing the clock domain. At the same time,some technologies of no-timing check, SDF file modification and constraint file addition are proposed,which overcome influence of metastable state phenomennon pro-duced by clock domain crossing on FPGA simulation and verification.
