CAJ | 학술논문

　　传统的微处理器由于内部有限的逻辑资源和外部固定的引脚封装，大大限制了应用范围。为此，在阐述微控制器的内部结构、存储器管理结构和指令集结构后，利用现场可编程门阵列丰富的逻辑资源，虚拟出传统微控制器的处理器核心，添加Wishbone总线，将处理器核心与通用外设连接构成一个虚拟的微控制器平台，并使用硬件描述语言Verilog和VHDL，自底向上设计AVR处理器核心，与通用外设互连组成系统，使用XILINX Virtex?Ⅱ Pro芯片进行板级验证。结果表明，实现了既定目标，与标准的微控制器兼容，系统运行稳定。该方法延续了传统微控制器的生命力，能使其得到更大发展。
　　전통적미처리기유우내부유한적라집자원화외부고정적인각봉장，대대한제료응용범위。위차，재천술미공제기적내부결구、존저기관리결구화지령집결구후，이용현장가편정문진렬봉부적라집자원，허의출전통미공제기적처리기핵심，첨가Wishbone총선，장처리기핵심여통용외설련접구성일개허의적미공제기평태，병사용경건묘술어언Verilog화VHDL，자저향상설계AVR처리기핵심，여통용외설호련조성계통，사용XILINX Virtex?Ⅱ Pro심편진행판급험증。결과표명，실현료기정목표，여표준적미공제기겸용，계통운행은정。해방법연속료전통미공제기적생명력，능사기득도경대발전。
Internal limited logic resources and external fixed?pin package of traditional microprocessors greatly limit their application range. The internal structure,memory management structure and instruction set architecture of micro control unit (MCU)are described. The abundant logic resources of field programmable gate array(FPGA)are used to virtualize the proces?sor core of traditional MCU. Wishbone bus is added to connect processor core with common peripherals to form a virtual MCU platform. Moreover,the bottom?up design of AVR core is performed with hardware description languages such as Verilog and VHDL,which is connected with common peripherals to build a system. Board level validation was carried out with XILINX Vir?tex?II Pro chip. The result shows that the set objective is achieved and the system which runs stable is compatible with standard MCU. This method continues the vitality of traditional MCU,and makes it further progressed.