现代电子技术
現代電子技術
현대전자기술
MODERN ELECTRONICS TECHNIQUE
2014年
14期
14-17
,共4页
信号源%DDS%FPGA%同步置位
信號源%DDS%FPGA%同步置位
신호원%DDS%FPGA%동보치위
signal source%DDS%FPGA%synchronous set
针对重离子加速器（HIRFL）的低电平相幅稳定系统，设计了以同步置位直接数字频率合成器（DDS）技术为基础的同步相位信号源作为系统的不同频、严相位的基准信号源。以FPGA芯片为核心，采用VHDL语言设计各功能模块，简化了设计过程，便于升级。经过电路设计、模块仿真和现场测试，验证了设计的正确性。测试结果表明：该系统具有可靠性高、精度高、稳定度高、频率范围宽、便于控制等优点。
針對重離子加速器（HIRFL）的低電平相幅穩定繫統，設計瞭以同步置位直接數字頻率閤成器（DDS）技術為基礎的同步相位信號源作為繫統的不同頻、嚴相位的基準信號源。以FPGA芯片為覈心，採用VHDL語言設計各功能模塊，簡化瞭設計過程，便于升級。經過電路設計、模塊倣真和現場測試，驗證瞭設計的正確性。測試結果錶明：該繫統具有可靠性高、精度高、穩定度高、頻率範圍寬、便于控製等優點。
침대중리자가속기（HIRFL）적저전평상폭은정계통，설계료이동보치위직접수자빈솔합성기（DDS）기술위기출적동보상위신호원작위계통적불동빈、엄상위적기준신호원。이FPGA심편위핵심，채용VHDL어언설계각공능모괴，간화료설계과정，편우승급。경과전로설계、모괴방진화현장측시，험증료설계적정학성。측시결과표명：해계통구유가고성고、정도고、은정도고、빈솔범위관、편우공제등우점。
A synchronous phase signal source based on synchronous set direct digital synthesis(DDS)technology as a vari-ous frequency and strict in-phase reference signal source of system was designed for low level phase and magnitude stabilization system of HIRFL. Taking FPGA as the kernel,the functional modules was designed with the VHDL language,which simplified the design process. It is easy to upgrade. The validity of system was verified by the circuit design,module simulation and test on spot. Performance test results show that the system has the advantages of high reliability,high precision,high stability and wide frequency range,and is easy to control.
