CAJ | 학술논문

RBF神经网络具有较强的拟合能力和稳定性，得到了广泛的应用。以FPGA芯片为核心器件，设计实现RBF神经网络。利用SOPC Builder设计硬件架构，通过添加指令，在NIOS环境下利用C语言进行设计，这样就解决了利用Verilog或VHDL设计消耗资源多和软件模拟耗时多的问题。最后以Altera公司的Cyclone IV系列芯片作为验证器件，结果表明该方法实现简单，可靠性强，消耗资源少。
RBF신경망락구유교강적의합능력화은정성，득도료엄범적응용。이FPGA심편위핵심기건，설계실현RBF신경망락。이용SOPC Builder설계경건가구，통과첨가지령，재NIOS배경하이용C어언진행설계，저양취해결료이용Verilog혹VHDL설계소모자원다화연건모의모시다적문제。최후이Altera공사적Cyclone IV계렬심편작위험증기건，결과표명해방법실현간단，가고성강，소모자원소。
RBF neural network with fitting ability and stability has been widely used. Based on the FPGA chip as a core de-vice,the RBF neural network is designed in this paper. The hardware architecture was designed by means of SOPC Builder,the added instructions and C language in NIOS environment. In this way,the problems existing in the design were solved,because they consume too many resources by using Verilog or VHDL to carry out the design and take much more time in software simula-tion. The Cyclone IV series chip of Altera Company was taken to perform the verification. The result shows that the method is simple,and has high reliability and less consumption of resources.