CAJ | 학술논문

制造工艺的快速进步给集成电路设计提供了广阔的空间,而发展较慢的设计能力导致难以对片上资源高效利用.目前,高性能处理器片上Cache普遍占到芯片总面积的一半以上,而如何高效、智能地利用片上Cache空间,构建高性能存储系统是处理器微体系结构研究的重要内容.分析了Cache数据污染和猜测执行对处理器性能的影响,并在此基础上提出一种基于数据Tag有效位分裂的无污染Cache访问控制技术—Pease,将原先D-Cache Tag中的一位数据有效位扩展为读数据有效位(RVB)和写数据有效位(WVB)两位,根据RVB和WVB值的不同组合对数据读写访问进行控制.不但充分保留了猜测执行的数据预取性,使污染数据透明化,写入数据时无需对污染数据进行替换操作,消除了污染数据对Cache效率的影响.Pease技术相对于baseline结构来说,IPC的提升幅度为1.05%~8.40%,平均提升4.04%;L1 D-Cache缺失率降低幅度为19.05%~48.16%,平均降低29.66%.
제조공예적쾌속진보급집성전로설계제공료엄활적공간,이발전교만적설계능력도치난이대편상자원고효이용.목전,고성능처리기편상Cache보편점도심편총면적적일반이상,이여하고효、지능지이용편상Cache공간,구건고성능존저계통시처리기미체계결구연구적중요내용.분석료Cache수거오염화시측집행대처리기성능적영향,병재차기출상제출일충기우수거Tag유효위분렬적무오염Cache방문공제기술—Pease,장원선D-Cache Tag중적일위수거유효위확전위독수거유효위(RVB)화사수거유효위(WVB)량위,근거RVB화WVB치적불동조합대수거독사방문진행공제.불단충분보류료시측집행적수거예취성,사오염수거투명화,사입수거시무수대오염수거진행체환조작,소제료오염수거대Cache효솔적영향.Pease기술상대우baseline결구래설,IPC적제승폭도위1.05%~8.40%,평균제승4.04%;L1 D-Cache결실솔강저폭도위19.05%~48.16%,평균강저29.66%.
Rapid progress of semiconductor fabrication provides capacious space for IC designs, but unfortunately, the slow de-velopment of design ability makes it difficult to utilize the on-chip resource efficiently. At present, more than half of die area of modern microprocessor is inhabited by cache. So, how to make use of cache space smartly and efficiently, and construct high performance memory system has become one of the most important content in processor architecture design. This paper analy-ses the impacts of cache data pollution and speculative execution to processor performance, and proposes a non-polluting cache accessing technique based on data tag valid-bit splitting, which is called Pease. The valid-bit in D-Cache tag is splited into two bits, read data valid bit(RVB)and write data valid bit(WVB). According the different RVB and WVB combinations, correspond-ing accessing strategies to D-Cache are applied. As a result, Pease technique not only preserves the prefetch ability of specula-tive execution, but also makes the cache polluting data transparent, which means that, in no empty cache line situation, conse-quent data can be written into D-Cache directly, but without need to perform cache replacement operation. In other word, Pease technique makes polluting data totally harmless to D-cache. Simulation result indicates that, relative to the baseline architecture, Pease technique improves IPC from 1.05% to 8.40%, averagely 4.04%, and reduces miss rate of D-Cache from 19.05% to 48.16%averagely 29.66%.