CAJ | 학술논문

采用提升结构的二维9/7离散小波逆变换模块是高清图像解码显示和实时处理的关键支撑技术。为实现电路模块的整体优化，在提升结构二维9/7离散小波逆变换标准算法的研究基础上，通过分析图像数据的输入输出顺序，结合器件模型提出一种翻转结构的优化算法。进一步地，给出了所提算法的一种多核并行VLSI结构：通过流水线技术将关键路径降为一级乘法器延迟；通过重组织数据流，处理N×N大小的图像仅需4N的中间缓存，从而在提升该模块速率的同时降低了中间缓存。基于Sparten6-xc6slx150t FPGA进行综合验证，结果表明该模块可稳定运行于166.34 MHz时钟速率。
채용제승결구적이유9/7리산소파역변환모괴시고청도상해마현시화실시처리적관건지탱기술。위실현전로모괴적정체우화，재제승결구이유9/7리산소파역변환표준산법적연구기출상，통과분석도상수거적수입수출순서，결합기건모형제출일충번전결구적우화산법。진일보지，급출료소제산법적일충다핵병행VLSI결구：통과류수선기술장관건로경강위일급승법기연지；통과중조직수거류，처리N×N대소적도상부수4N적중간완존，종이재제승해모괴속솔적동시강저료중간완존。기우Sparten6-xc6slx150t FPGA진행종합험증，결과표명해모괴가은정운행우166.34 MHz시종속솔。
The circuit module of 2D lifting-structure based 9/7 Inverse Discrete Wavelet Transform(IDWT)is the key technology of the decoding and display and the real-time processing of the high resolution image. To improve the global performance of the circuit module, the principle theory of 2D lifting-structure 9/7 IDWT is studied. With the characters of the image data flow studied, the novel flipping-structure algorithm is proposed based on the circuit model. Further, the par-allel processing VLSI architecture of multi-processor based on the proposed algorithm is designed, in which the critical path is reduced to one multiplier by pipeline and only 4N transfer memory is needed for a N × N image by the data flow re-organization so that the memory consumption and the processing speed are improved simultaneously. The circuit module is synthesized and verified on Sparten6-xc6slx150t FPGA, which shows that the system can operate smoothly at 166.34 MHz clock rate.