现代电子技术
現代電子技術
현대전자기술
MODERN ELECTRONICS TECHNIQUE
2015年
12期
126-128
,共3页
可编程增益放大器%恒定带宽%低功耗%射频收发机
可編程增益放大器%恆定帶寬%低功耗%射頻收髮機
가편정증익방대기%항정대관%저공모%사빈수발궤
PGA%constant bandwidth%low power consumption%RF transceiver
随着无线智能终端功能的不断丰富，可穿戴设备、无线传感器网络、无线手持终端等得到了快速发展，如何降低射频收发机的功耗成为了越来越突出的问题。作为射频收发机重要模块的可变增益放大器，其电路设计的好坏往往直接决定了射频接收机的总体性能，在此研究并设计一种低功耗恒定带宽可编程增益放大器，该可编程增益放大器主要由2个Gm跨导单元、压控电流衰减器以及电阻阵列构成。采用两个高线性度Gm跨导单元有效减小芯片面积和功耗，并且增益变化不会导致带宽变化。在TSMC 130 nm CMOS工艺下进行了后仿真验证，实验结果显示该可编程增益放大器在1.2 V电源电压下以400μA的电流消耗实现了增益调节范围0~40 dB，增益连续调节，线性度OIP3为18.84 dB，性能良好。
隨著無線智能終耑功能的不斷豐富，可穿戴設備、無線傳感器網絡、無線手持終耑等得到瞭快速髮展，如何降低射頻收髮機的功耗成為瞭越來越突齣的問題。作為射頻收髮機重要模塊的可變增益放大器，其電路設計的好壞往往直接決定瞭射頻接收機的總體性能，在此研究併設計一種低功耗恆定帶寬可編程增益放大器，該可編程增益放大器主要由2箇Gm跨導單元、壓控電流衰減器以及電阻陣列構成。採用兩箇高線性度Gm跨導單元有效減小芯片麵積和功耗，併且增益變化不會導緻帶寬變化。在TSMC 130 nm CMOS工藝下進行瞭後倣真驗證，實驗結果顯示該可編程增益放大器在1.2 V電源電壓下以400μA的電流消耗實現瞭增益調節範圍0~40 dB，增益連續調節，線性度OIP3為18.84 dB，性能良好。
수착무선지능종단공능적불단봉부，가천대설비、무선전감기망락、무선수지종단등득도료쾌속발전，여하강저사빈수발궤적공모성위료월래월돌출적문제。작위사빈수발궤중요모괴적가변증익방대기，기전로설계적호배왕왕직접결정료사빈접수궤적총체성능，재차연구병설계일충저공모항정대관가편정증익방대기，해가편정증익방대기주요유2개Gm과도단원、압공전류쇠감기이급전조진렬구성。채용량개고선성도Gm과도단원유효감소심편면적화공모，병차증익변화불회도치대관변화。재TSMC 130 nm CMOS공예하진행료후방진험증，실험결과현시해가편정증익방대기재1.2 V전원전압하이400μA적전류소모실현료증익조절범위0~40 dB，증익련속조절，선성도OIP3위18.84 dB，성능량호。
With increasingly rich functions of wireless intelligent terminals,rapid development of wearable devices,wire?less sensor networks and wireless handsets has been achieved. However,how to reduce the power consumption of RF transceiver has become a more and more serious problem. As a core module of the RF transceiver,the programmable gain amplifier(PGA) plays a crucial role,and its circuit design level often determines the total performance of the RF transceiver. A novel PGA with low?power consumption and constant bandwidth is designed in this paper. It is composed of two Gm transconductance cells,a voltage?controlled current attenuator and a resistor array. The die area and power consumption are reduced effectively by the two Gm transconductance cells. The PGA bandwidth is independent of the gain setting. The PGA was simulated in TSMC 130 nm CMOS process. The simulation results show the PGA can realize 0~40 dB gain adjustment with less than 400 μA power con?sumption under the condition of 1.2 V supply voltage,and its linearity OIP3 is 18.84 dB.
